Still confused about memory bandwidth, though. The RAM can push out 6400, which is 800 X 8.
The MB can handle a throughput of what -- if it's running at a 400 mhz bus speed, isn't that 1600 FSB? So do you multiply that by 8 as well to get a total throughput of 12800?
And how do you account for the fact that each module of RAM will be pushing that much? So if the MB can accept 12800, and each RAM module pushes out 6400, then 4 GB of ram on 2 modules would be 12800. IF you add 4 more GB of RAM, you'd need 6400 X 4 or 25600 of bandwidth for all the data it can push, right? So the MB would be a bottleneck in that instance?
So my number was correct for the MB, it can handle throughput of 12800?
And how is it exactly that the RAM gets to 12800? Are you saying that each module is 6400 one-way, or 12800? And that I don't add the capacity of all the ram together (so it would not be 12800 for each module, or 51200 for 4 modules?)?
All the ram runs at 6400, it doesn't multiply by how many sticks you have. The 6400 is how many MB/s the ram transfers, the actual bus speed is 400mhz, and it doesnt change based on the amount of sticks you have.
Actually it does double the bandwidh of RAM if you running dual channel. That's the point of dual channel. But 2 dual channel kits will still count as 12.4 GB/s (in case of 400 ram bus).
I think the bottlneck will be actually your memory controller on the motherboard.
I have P5Q Pro, E8400 and 4 GB
Running 1:1 at 400 mhz 4-4-4-15 timings
Theoretically the bandwidth of FSB to MCH (memory controller) is 12.4 GB/s and RAM to MCH 12.4 GB/s, but in synthetic ram bandwidth tests, ie sis sandra, I get max 7 GB/s (about 57% efficiency). This seems the maximum I can squeeze without rising the FSB. Rising FSB will also increase max bandwidth, so efficiency wont be better. I wish I knew why this bandwidth loss... timings? 7 GB/s on tRD 8 (the minimum my sys boot with at 400 FSB), and AI clock twister on "Stronger".
I think if you put 8 GB this wil stress the MCH even more, and you will get even less bandwidth. But this is just in my theory.