Can AMD make K10.5 a octo-core?

[Amiga500]

There is supposed to be a version of K10.5 (Deneb) without any L3 cache.


Obviously, this saves a lot of die space. I do remember reading the K10 arch was designed so MCM could be built to 8, 12 or 16 cores.


Question is, can AMD do it at 45nm with Deneb and would there be any benefit to it?

 

[homerdog]

Hopefully AMD will get the quads working right before they move on to 8. Even some new dual cores to compete with Wolfdale would be nice.

To answer your question, they probably could do it, but the benefits, well...

If I recall correctly, the TLB errata BIOS workaround partially disables the L3, so if you want a ballpark estimate of this Deneb's performance check out some of the TLB patch articles like this one.

 

[sailer]

I agree with homerdog. AMD probably could do it, and so could Intel for that matter. Better questions might be will they do it, and why bother. In the home use arena, quads are hardly being used now, so there is no sense at all in providing even more cores. Only the business world would see any possible advantage for the time being. Beyond that, as core numbers are increased, failure rates will increase. That's the main reason for the AMD triple core chips. They are really quads that have a bad core. From an economic standpoint, its much better to increase the number of chips then to increase the number of cores on a chip.

Again, as homerdog pointed out, AMD's time would be better spent making their quads work better and perhaps putting out some dual core chips instead of trying to build bigger chips.

 

[zenmaster]

There is supposed to be a version of K10.5 (Deneb) without any L3 cache.


Obviously, this saves a lot of die space. I do remember reading the K10 arch was designed so MCM could be built to 8, 12 or 16 cores.


Question is, can AMD do it at 45nm with Deneb and would there be any benefit to it?

I think AMD will need to lower the Power Envelope Quite a bit to do this.
They will be dropping from 125w/130w to 95w w/45nm.
However, going to 8 cores will raise this to as high as 190w.

Considering very few items scale to 4 threads, much less beyond they will be better served by increasing the speed of each core rather than adding cores.

 

[basketcase]

They could. But, they definately don't need to.

 

[spearhead]

the propus the deneb without l3 cache still could be a nice chip. price preformance wise. i dont think the preformance hit is as dramaticly in some benchmarks as seen with the tbl patch. no l3 should allow higher clockspeeds and less power consumption.yet the deneb 45nm should be better off with the 6mb l3 cache it should come with. and later maybe around first to second Quarter next year the k10.5 with 1mb per core and 12mb l3 cache should be lined up. id rather want to see more l2 cache on the phenom before they moveon to more cores. many threats dont use more then 1 or 2 cores anyways, 8 cores is even less supported unless amd implements an instrustion that manualy manipulates an unoptimized task to take advantage from all cores that is.

 

[Reynod]

The TLB workaround did more than "just disable" the L3 cache - that isn't a valid comparison to say just look at the performance hit we see there.

Several articles detail that issue fully.

You would probably find minimal L3 cache would impact heavily on virtualisation I suppose.

I'd imagine it would have a similar effect to the performance differences found with duron / semperon.

The bigger cache on K10 seems to have had a smaller effect wrt gaming etc than many would have liked / wished.

core2 has a better cache system therefore the IPC is generally higher.

cahce isn't going to be the answer for K10.

People are barking up the wrong tree.

Architecturally there need to be changes.

Plus the latency is just miserable.

Core2's L1 / L2 latency is tighter than US spending on health.

 

[jimmysmitty]

Naitive....probably not without some major work. Double Cheese burger? Maybe as long as the IMC doesn't interfere.

Best thing for AMD, as has been said before, is to make their current chips work better, i.e. compete on a even level IPC, and make some dam dual cores.

I am suprised AMD has not had anything new in the dual core market yet besides a few refreshes of K8.

But thing is we don't run AMD. Some crazy minded execs who obviously have not managed it right do.

 

[gallag]

have AMD not already said they will go mcm for octo (i.e copy Intel doing it the way they said was wrong).

 

[TechnologyCoordinator]

Hopefully AMD will get the quads working right before they move on to 8. Even some new dual cores to compete with Wolfdale would be nice.

To answer your question, they probably could do it, but the benefits, well...

If I recall correctly, the TLB errata BIOS workaround partially disables the L3, so if you want a ballpark estimate of this Deneb's performance check out some of the TLB patch articles like this one.

Agreed.

 

[B-Unit]

Why do we need more dual-cores? The software is coming, embrace the future. Betcha there wont be a dual-core Nehalem chip. Why would AMD waste precious resources to develop a new dual core when those resources would be far better spent on improving the quad and developing octo and up. Remember that the server arena is where AMD is really interested in playing, and an octo-core there makes alot of sense.

 

[MarkG]

Betcha there wont be a dual-core Nehalem chip.

http://www.realworldtech.com/page.cfm?ArticleID=RWT040208182719&p=9

"Next up are Auburndale, Havendale and Clarksfield, which are a dual-core desktop, a dual-core mobile and a quad-core mobile processor."

Intel will sell what sells, though those dual-core chips may have hyperthreading to allow them to run four threads at a reasonable speed.

 

[B-Unit]

Wow, am I the only one who thinks it doesnt make sense to make a dual core out of a native quad design?

 

[Slobogob]

Wow, am I the only one who thinks it doesnt make sense to make a dual core out of a native quad design?

What else would you do with a native quad core that has two broken cores? Throw them away????

 

[B-Unit]

If i have 2 broken cores, id go back to the drawing board as my design must have some pretty big problems.

 

[Wisecracker]

If i have 2 broken cores, id go back to the drawing board as my design must have some pretty big problems.

Wow, am I the only one who thinks it doesnt make sense to make a dual core out of a native quad design?

As pointed out by Spearhead the overwhelming majority of software on the desktop cannot make use of 2 cores, much less 4 - 6 - 8 - 12 - 16 or 32 cores.

I would expect that the AMD dual core 45nm will clock higher, run cooler and operate on split power planes over HT3 (see the Puma mobile platform)

http://techreport.com/articles.x/14858

 

[ryman554]

Wow, am I the only one who thinks it doesnt make sense to make a dual core out of a native quad design?

no, but you're asking the wrong question.

Does it make sense to make a 4-, 8-, and 2-core CPU out of a modular deisgn?

 

[B-Unit]

Well Ill be the first to admit I know next to nothing about fab tech, but it was my understanding that a fab was capable of producing a single design and changing that design required massive ammounts of $$ and effort. It would seem that if your going to tool for a quad core design, it would be counter-productive to swich back to a dual core design.

 

[Slobogob]

If i have 2 broken cores, id go back to the drawing board as my design must have some pretty big problems.

As it looks they have to do just that with Phenom.

 

[amdfangirl]

^ Yes, and those have been delayed, yet again...

 

[archibael]

Well Ill be the first to admit I know next to nothing about fab tech, but it was my understanding that a fab was capable of producing a single design and changing that design required massive ammounts of $$ and effort. It would seem that if your going to tool for a quad core design, it would be counter-productive to swich back to a dual core design.

Not really.

Fab masks cost on the order of a couple million bucks for a set, but that's a pittance given the money involved in sales of the chips. Most of the sunk costs into a design are the years of man-hours doing the VHDL and physical layout and validating it, and if you've done the work up front to design your chip in a modular fashion, you can essentially "chop off" the parts you don't need for a 2-core part and generate new masks. Like I said, it's a couple of million bucks to get through, but your actual redesign money is essentially zero, and you now have a smaller die... which means you can get more die per wafer, which means your costs are lower and your profits are higher.

If there's a market which will be satisfied with and will pay good cash for dual core, it's a waste of silicon to draw your dual cores from only the quad-core dice which do not yield-- or, worse, to purposely disable two cores to meet the dual-core demand. Having a good modular design puts a lot more overhead on the design side of the process, and requires more masks to do the job, but ultimately saves so much cash that it's worth it.

 

[B-Unit]

Ahhh, i see. Well that would make sense now.