SOI

There isn't any real confusion over SOI. I admit, I didn't follow SOI vs. HK/MK before discussions here, but the thing that people are arguing over is whether it hinders Phenom at 65nm, whether Deneb at 45nm with more pipelines will be as successful as Penryn and what AMD and IBM's next HK/MK 45nm process will bring to the server and desktop market. For the most part, I haven't found any articles that are recent discussing the benefits of SOI alone, which is why it's probable it's being phased out or hybridized.

I trust IBM's research division. Just because Intel doesn't use SOI today does not make it a failure. Still, I think we'll see more hybrids of materials and processes on the desktop in future years, from both AMD and Intel. Perhaps that's why SOI and HK/MK are being blended for future AMD CPU's -- SOI brings cooler CPU's and HK/MK allows for higher clocks with fewer pipelines. Anyways, I'll let the grad students and professionals argue that one. I'm into desktop game and video performance as well as ethical competition in the marketplace that's a win win situation for everyone (so no more Intel OEM rebate dodgy deals).

An understanding of how SOI is made helps to clear up some misunderstandings.
node is not die thickness
MG/HK and SOI are not mutually exclusive
How it affects capacitance
And therefor why it is less important to Intel
How it might affect the cold bug
What impact it could have on higher speeds.

To be honest, I would also like to see more posts about how stuff works, and less fanboy crap.

Jimmy is one of the people who I hope will read the article. Sometimes he seems like a pain in the butt kid I kind of think he'll be okay.
We see HK/MG a lot, but i wonder howmany people know what it means.
Why did they go from low K to high K?
What material does MG actually mean?
Here's a hint. Intel's silicon gate technology on 45nm is the best in the world.

The leakage issues from heat burst, and a poor IPC all contibuted to Intel going/looking to HK/MG or something thatd pervent the leakage. Wonder how a C2D would run strictly using SOI?

Not much of a kid but yea I am ok.

I look at it this way, SOI had potential but is obviously going to hit issues at either 45nm or beyond hence why AMD is going SOI 45nm and then HK/MG on 45nm later.

I do know that the reasoning to move to high k is to help control leakage beyond 65nm. Now the MG is based on Hafnium instead of Silicon. It gives the same properties but can be streached thinner with less leakage.

I will read on the article a bit more when I have time.

Actually from what I understand, from AMD's own website and tech stuff. 45nm Shanghai/Deneb is suppose to be a SOI/LowK metal gate hybrid process.. They're suppose to be using a lowK germanium transistor process on the first 45nm parts then moving to IBM's HK/ metal gate after that.

We just need one of those engineering types to translate one of the tecky articles into something meaningful so we can understand it.

I for one need some pictures ... just still ones ... no sound or moaning needed thanks.

A comparison would be good.

With the huge headroom of the current Intel process I would imagine they are probably having to render some of the good units (cripple them) just to make celery and low end / small cache chips.

I can't recall anyone posting a conroe or penryn yet that wouldn't clock to 3 Ghz at least ... most without a voltage boost. Please correct me if I have missed a number of them ??

It has got to tell you a lot about the quality of their process.

This seems to be where poor old AMD has failed ...

Still ... providing the layoffs don't include the people making the chips (not the telephone sanitizers / marketing team) they may yet get there.

I must admit it is good that the thread is very civil ... all the best to each of you !!

It isnt SOI. Just read the link from the OP. From what I remember, its a pure silicon based process, cant remember alot about it tho...Strained silicon was used. Heres something thats older, from '06 I believe, but still stands today. "What about other manufacturers%u2019 use of %u201Csilicon on insulator%u201D (SOI)?
Intel%u2019s superior transistor performance and leakage have been achieved by meticulous engineering of %u201Cbulk CMOS%u201D techniques, which offer the highest performance and best value to our customers. SOI adds substantial costs and complexity to the process. A comparison of published transistor switching speeds shows Intel%u2019s bulk transistors to have faster switching speeds at comparable leakage currents compared to the best published numbers on SOI transistors. A more troubling issue is that SOI has higher %u201Cthermal resistance%u201D than bulk CMOS. As a result, SOI transistors are forced to run at temperatures higher than necessary. Higher operating temperatures could cause long-term reliability problems." That was their evauluation in '06 on SOI, and it hasnt changed any

NP. Im just glad to read and learn about this process as well. I dont think SOI has completely played itself out, but its getting close. One thing that I read was that AMD plans on going with a different litho process, which will make the transistors much more efficient, which if they pull it off, then using SOI wont hurt them as much, tho eventually theyll have to go HK/MG

Please do. Then you may understand that SOI is just a sublayer built into the wafer. It can be there @ any node, and with any type of transistor (it is better with nodes <130nm however).
AMD may stop using SOI in 09, but only because it would require a rework of ATI's design system. Thier HK/MG will most likely be on SOI wafers.

As to the hafnium, well, no, the hafnium is added to the gate oxide. http://www.betanews.com/article/In [...] 1169872301. It has a higher insulation value, at a thinner cross-section. With a thinner cross-section, the voltage from the gate is able to supply more force to push electrons/wholes to the drain. The better insulation allows the gate to hold it's voltage better.
The "metal gate" uses nichel, in it's silicon because silicon alone would not have enough potential to properly trigger source to drain flow. ( at current levels that Intel's process can achieve) That metal gate is actually NiSi.
Without the metal gate, AMD does not need HK. They can incorporate a slightly higher insulation factor in thier gate oxide by including nitrogen in it. This would allow them to thin down the gate oxide to the level they need for thier process's potential.
I would expect that to allow better power saving rather than much faster speed.

Sorry, no pictures, just a little info.
Like all wafers, Intels bulk silicon is made by growing silicon crystal. In any process like that, you are going to get some bad spots, where the structure is not quite up to snuff. The structure is usually best at the center, not as good further out.
I'm not familiar with how Intel's strain process works, but it ia also likely to be a source of small flaws.
At 45nm, Intel is using a double exposer litho process. This can also cause transitor failures.
Once they start the litho process, the wafer is masked and washed and baked, masked and washed and baked, again and again. The smallest speck of loose silicon or dust can damage a transistor.
You may have seen a comleted wafer. You may have noticed that while the transistors cover the whole wafer, many on the outside look like they are not complete chips.
Just a few examples of where celerons come from.

If anyone is interested in a little history, this is my favorite article
http://www.pldos.pl/bogus/hardware [...] erview.htm
It's an interview with the inventor of silicon chip technology.

IBM gets a lot of the credit. The R&D guys are paid by a consortium that is paid by Sony, Hitachi, AMD, NEC, Infineon, Samsung, Chartered, and IBM. Not all players are in for all the projects, but immersion includes most of them.

Some is done at East Fishkill, some at Dresden. Most is done at universities around the world.

endyen ... thanks for the article.

Pentium M was a big step for Intel ...

I wonder ... was it a bigger step in terms of IPC from P4 to M than M to Core2?

Assuming the same clock speed that is?

Actually, those wafers you always see with partial chips on the outside edges are test wafers. The fab guys would know better than me, but for production use, I believe they optimize the litho process so it doesn't even image those parts of the wafer. (The litho tools don't image the entire wafer in one shot - they image a few chips then step over to do the next few.) Litho tools are the most expensive in a fab (and getting much worse with every new generation). You can bet they strive to use them as efficiently as possible.