amd native six core and the final cylon

[reconviperone1]

Just read this a few minutes ago, it seems amd is on the offensive with some of the recent announcmentshttp://forums.vr-zone.com/showthread.php?t=264787
As for the final cylon(which has nothing to do with cpu's) it's a character named bulldog, that was on one episode

 

[jimmysmitty]

Hmmm.... well judging by how well AMD has kept to their roadmaps for the past year or so, its hard to see what this will do.

So they clearly want to take a stab at Intels Dunnington but if Shanghi is just a 45nm shrink of Barcy, I am doubting to see major performance improvements.

But I guess we will see. I also love how they want to go with the 2x6=12.. Funny how AMD critisized Intel for it and now they are planning the same thing.

 

[dobby]

dont lose any sleep please, unless you have AMD stocks

 

[Reynod]

Thats it then ...

Intel are the Cylons and the ragtag fleet from the 12 colonies are AMD.

Ruis even looks like Adama.

In last weeks episodes they lomotomised a heap of the raiders ... interesting comparison to the P3's to Pentium M's there.

The metal models are the P4's.

Number 6 has got to be an E8400 ... her temp sensor is a bit wonky.

I leave the rest of the models to you.

 

[MU_Engineer]

Hmmm.... well judging by how well AMD has kept to their roadmaps for the past year or so, its hard to see what this will do.

They have somewhat kept to the details of the actual CPUs that shipped, but their dates were just way off. I'm not surprised at the delays as the quad-core K10 was a very ambitious project. Even Intel didn't want to touch a monolithic quad-core CPU with an IMC until the end of their 45 nm run, let alone at 65 nm.

So they clearly want to take a stab at Intels Dunnington but if Shanghi is just a 45nm shrink of Barcy, I am doubting to see major performance improvements.

There should most certainly be performance improvements, at least as far as absolute performance is concerned. The 65 nm K10s are very much clock speed limited due to heat production (at least in shipping units) and 45 nm will allow for higher clock speeds. Shanghai will also triple the L3 cache, which may very well give a decent bump in performance clock-for-clock as well. The big L3 cache in Dunnington may or may not provide much of a gain, depending on its latency and the particular applications being used.

But I guess we will see. I also love how they want to go with the 2x6=12.. Funny how AMD critisized Intel for it and now they are planning the same thing.

It is called marketing. Marketers are like politicians and lawyers- they feel completely free to completely contradict what they said a few minutes ago and think nothing of it. Intel criticized AMD's monolithic core designs and said their FSB was good enough but now they are going to a monolithic core with an IMC just as AMD had. And I bet they tout the core design and IMC in their future ads, too.

 

[Reynod]

AMD needs a faster cache ... not a bigger one.

That's the problem essentially isn't it MU ??

Even with the IMC at 2Ghz is isn't as good as the X2 / Opti IMC that runs at core speed ... plus the latency is all over the shop.

Sounds like it needed another 12 weeks with the Engineers.

I guess they planned for the whole die to run much faster but with the heat generated from the 65nm process they had to slow the centre down because of stability problems.

That would be my interpretation.

If the IMC ran at core speed with reduced latency then Barcelona's performance would have been higher ... perhaps as high as they bragged.

Unfortunately issues with the process and heat meant the production chip needed to be slowed down in key areas for stability.

AMD might be good at chip design but making them ... well ... maybe they should get asset light??

 

[reconviperone1]

Thats it then ...

Intel are the Cylons and the ragtag fleet from the 12 colonies are AMD.

Ruis even looks like Adama.Never noticed that your right,LOL

In last weeks episodes they lomotomised a heap of the raiders ... interesting comparison to the P3's to Pentium M's there.

The metal models are the P4's.

Number 6 has got to be an E8400 ... her temp sensor is a bit wonky.

I leave the rest of the models to you.

 

[blackpanther26]

lso apperantly HT3.0 was a waste on the 65nm CPU's

However, where as Barcelona had its HyperTransport 3.0 clock generator fused off, Shanghai will once again attempt to get HT3.0 right.

resource http://www.dailytech.com/Dodecacore...fficially+the+Multicore+Race/article11531.htm

 

[reconviperone1]

lso apperantly HT3.0 was a waste on the 65nm CPU's

However, where as Barcelona had its HyperTransport 3.0 clock generator fused off, Shanghai will once again attempt to get HT3.0 right.

resource http://www.dailytech.com/Dodecacore...fficially+the+Multicore+Race/article11531.htm

Sounds like 65nm was a waste anyway, but seems like they are on track