That article makes absolutely no sense, I tried reading it twice to make sense of it. And it was still like wha?
Something to do with those extra pin's on the processor. Even my 780g mobo support's it. I guess if i had the 9850 in my rig when this tech get's released it's just a bios flash away.
You get 3.2ghz with the new chipset!
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12,450 3DMark's06
AMD X2 6000+@3.3
Vista 64 bit
Gigabyte..AMD 780G
The issue with the sb600 - sb700 - sb7xx (and OC instability) is related to the phase lock loop (PLL).
All AMD board timing is referenced to the internal cpu clock. The clock distribution is balanced so that each signal clock arrives at every endpoint simultaneously regardless of bus speed.
Every signal along every trace is in fixed relationship to the phase of the "reference" signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising and/or lowering the frequency. In this way regardless of frequency (PCI, PCIe, USB, HTT, CPUCLK, NB, SB, etc) the timing of each cycle starts and ends in a congruent fashion.
The signals are fashioned and fixed by their 'skew characteristics' (think of this as variable PLL signals running with the fixed PLL). When the different signals are mucked-up the variance between the fixed PLL and the varible PLL signals is called 'jitter'.
When OC'ing the Phenom with the mucked-up south bridge PLL I believe the jitter accumulation became too great leading to instability and system failure. I gather this because all the sb7xx fixes involve the sb PLL timing.
The issue with the sb600 - sb700 - sb7xx (and OC instability) is related to the phase lock loop (PLL).
All AMD board timing is referenced to the internal cpu clock. The clock distribution is balanced so that each signal clock arrives at every endpoint simultaneously regardless of bus speed.
Every signal along every trace is in fixed relationship to the phase of the "reference" signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising and/or lowering the frequency. In this way regardless of frequency (PCI, PCIe, USB, HTT, CPUCLK, NB, SB, etc) the timing of each cycle starts and ends in a congruent fashion.
The signals are fashioned and fixed by their 'skew characteristics' (think of this as variable PLL signals running with the fixed PLL). When the different signals are mucked-up the variance between the fixed PLL and the varibale PLL signals is called 'jitter'.
When OC'ing the Phenom with the mucked-up south bridge PLL I believe the jitter accumulation became too great leading to instability and system failure. I gather this because all the sb7xx fixes involve the sb PLL timing.
That's my story and I'm stickin' to it ...
LoL fair enough.
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12,450 3DMark's06
AMD X2 6000+@3.3
Vista 64 bit
Gigabyte..AMD 780G
I can't wait to see some benchmarks of this. It seems such a weird strategy to sell motherboards based on what speed your cpu will run. I mean what was AMD waiting for, for the past year they've been churning out underclocked phenoms and they just now decide to throw out this six hidden pins concept? I guess they needed to announce something in the wake of anands nehlalem preview.
So I was reading through the article and it says that the SB 600 chips don't have this feature, then it says that the 7xx series northbridge chips support this. Well, all 790FX, 780G motherboards have the southbridge 600 chip. The article says that you need a special southbridge chip to achieve this magical overclock, an SB700 for +200mhz and an SB 750 for 400mhz. I kinda get it, the article is very poorly written though and still up for interpretation.
My understanding is, when AMD launches the SB 700 and 750 chips for motherboards, we will finally see this magical auto OC.
I guess?
I can't wait to see some benchmarks of this. It seems such a weird strategy to sell motherboards based on what speed your cpu will run. I mean what was AMD waiting for, for the past year they've been churning out underclocked phenoms and they just now decide to throw out this six hidden pins concept? I guess they needed to announce something in the wake of anands nehlalem preview.
I don't think this was in response to Anand's review. In fact I believe that Fudzilla and the Inquirer reported on this several weeks ago. I think most people just didn't take it seriously at the time since those aren't exactly the most reputable sources on information.
So its not a thermal issue at all, but a timing issue created by the sb?
I imagine the thermals have an impact but the southbridge PLL problems have been a big deal.
A slight bump in voltage to the sb(600) PLL seem to get folks another 100-200MHz. SB700 was a little worse for OC'ing from what I understand. SB750 is the 'big fix' for all the sb timing issues.
I'm not sure what the change in BIOS is all about. I think some vendors (like MSI on the 790fx) had the sb PLL voltage adjustments but other vendors did not.
AMD just doesn't have the resources to work out all the kinks before launches kinda making beta testers out of early adopters. If the article is correct it's good news for us all. 3.2GHz Phenoms on a consistent basis is a pretty big deal ...
When the 780s were released, everyone had it bad on the reuse of the 600sb. Then I saw the 700 and it wasnt much better. So this looks really nice
I think I read in a report that the sb700 timing problem was so bad the chips had to have a crystal installed in them to bring everything back to 'phase' - kinda sounds like FUD to me but who knows?
So I was about to ask, which mobos have the SB700 chip, so I looked before I asked and found that only the 780G mobos seem to have SB700, 790X & FX have SB600. Kinda weird, but lets see this SB750 chip!
+400mhz ftw
