I guess he would need to use Phenoms to match the quad Xeons, but the ultimate conclusion is correct, or am I in left field?
Well, a K8 has 3 hypertransport links.
In a 4P board, that means 1 die is left out (1 hypertransport link must go to main memory)... increasing latency in passing information. (i.e. data from die 0 going to die 4 requires twice the time as data from die 0 to die 1.
That bottleneck would not exist in 2P K10s.
Therefore the amount of time spent shuttling data *might* drop quite considerably.