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What Makes Core 2's So Much Better Than the X2

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July 12, 2008 2:12:15 AM

I know that Core 2's are alot faster than X2's; however, does anybody know why? From a technical perspective why can't AMD compete with the performance?

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Anonymous
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July 12, 2008 2:16:37 AM

its because of architecture and the efficiency in which the instruction sets are performed... I don't know actual technical reasons... you MIGHT be able to find an actual intel diagram or something... but i doubt it
July 12, 2008 2:37:33 AM

Before Wolfdale, it was just a better chip. Better architecture, can do more in a cycle and more efficient, now it's not only that, Wolfdale has better instruction sets and 45nm compared to X2's 65nm
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July 12, 2008 2:52:45 AM

The Core 2 is a radically reworked Pentium-M core CPU that has a larger IPC and high-performance low-latency cache. There are other architectural improvements as well which include, amongst other things, a 128-bit SSE engine.
July 12, 2008 3:09:00 AM

Courage!
July 12, 2008 3:11:11 AM

Another thing is Intel is now using High K materials while AMD bet on IBM's SOI... So the Intel's tend to hit higher clocks. I think the Athlon 64 if it was built on High K rather then SOI would be the faster CPU at least in pure Mhz (only my thinking and my thinking has been known to be wrong in the past)

Anyway thats only part of the story and I am sure I am confused in some way or another :) 
July 12, 2008 3:22:38 AM

JonathanDeane said:
Another thing is Intel is now using High K materials while AMD bet on IBM's SOI... So the Intel's tend to hit higher clocks. I think the Athlon 64 if it was built on High K rather then SOI would be the faster CPU at least in pure Mhz (only my thinking and my thinking has been known to be wrong in the past)

Anyway thats only part of the story and I am sure I am confused in some way or another :) 


That is quite possible. Rumors have been floating around that AMD will drop SOI for high K, but those are merely rumors.

As for the OP's quesiton - haven't a clue, to be honest. It could be the redesigned architecture or the materials being used, or Intel just being very lucky this go around, or a combination of all the above. Who knows?
July 12, 2008 3:35:04 AM

i see flames in the near future.....
But anyways.
Right now, the Core 2 series is better for a number of reasons, which really haven't been disclosed. One may be the high-k metal gates, as Intel is advertising that they allow more throughput and less loss. The smaller die size offers better thermal efficiency, opening up the doors to have higher clock speeds. (The die size isn't really directly inversely proportional to clock speed.)
I know I'm going to get flames for this, but if AMD really wanted to make their processors faster, they should remove the L3 cache, and increase the size of the L2 cache since it is faster. Like, put 8MB of L2 cache on the phenoms, and get rid of the L3 cache. (The Intel QX9770 has 12MB of L2 cache, which would give a noticeable increase in speed.) If i recall correctly, AMD's new Deneb series will have an L3 cache processor, and a processor without L3 cache.
And honestly, the Core 2's are extremely far ahead of the X2's. The X2's were released in August of '05. The Core 2's were released 11 months later in July of '06. The X2's are a slightly older technology, and AMD hasn't gone back and redone the architecture.
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July 12, 2008 3:38:37 AM

To the OP, look for article that came out when the C2D first came out. Toms and other sites went really in depth about it, you should find more then you ever wanted to know.

As for SOI vs High K, didn't I read something that said IBM had both working on 45nm samples? My memory might be off about it, but I think I read something about a 45nm surprise that IBM has. (no 100% guarantee that AMD will pick it up, but I'm sure they will certainly try.) I remember reading that IBM had issues with their SOI gates at 45nm, so they had to change things up a bit. I thought the article said metal/high K gates, but I honestly don't remember.
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July 12, 2008 3:40:38 AM

Seeing as they have an IMC, having large amounts of L2 cache won't benefit AMD as much as it does Intel. Having L2 cache hits is faster then having to go to the memory, but seeing as AMD chips have a HTT link to the memory and no FSB, its not hurting them as bad.
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July 12, 2008 3:49:43 AM

NMDante said:
That is quite possible. Rumors have been floating around that AMD will drop SOI for high K, but those are merely rumors.

As for the OP's quesiton - haven't a clue, to be honest. It could be the redesigned architecture or the materials being used, or Intel just being very lucky this go around, or a combination of all the above. Who knows?


According to what IBM and 10 other (including AMD) companies are doing they are shooting for the same style of HK/MG as Intel has but at 32nm. The rumor was that 45nm will have a refresh in 2009 where it uses HK/MG. I higly doubt that will come as it is up to IBM, so AMD has to wait, really in order to get something new.

The main reason behind Core 2 being better is that Intel made Core 2 to be better than Athlon X2. Its kinda how Athlon 64 was made to be better than Pentium 4. And what others have said is correct, Core 2 is based off of the Pentium M which got its main build from the Pentium 3 Coppermine core which was great but at the time did not allow for high clock speeds (not much past 1GHz anyways).

Core 2 integrated all the stuff from Netburst that has work (not the long pipelines or low IPC) and put out a great CPU. And Core 2 does have a higher IPC than Athlon X2.
July 12, 2008 8:18:26 AM

Hi,

The Core 2 has an "out-of-order execution" model of instruction issue. Instructions can be issued continously as long as they are not dependent on the result of previous instructions, branching instructions have advanced speculative execution (effectively guessing whether to branch or not). The C2D architecture also is Superscalar in a similar way to the K8/K10 issuing batches of microinstructions each clock. In order for out-of-order execution to work microinstruction state changes must be commited in-order a technique that was being researched in the 1990's (a buffer is used to store changes until they can be safely committed, was called a "Future File" in academic papers).

So the real killer for AMD is that the C2D archiecture is chomping away on multiple instructions almost every clock while the K8/K10 architecture will be pay for load cache misses, etc. and will really heavily on Compiler optimization to issue 3-4 microinstructions per clock.

Bob


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July 12, 2008 2:06:54 PM

Pretty much what Bob said ...

The Chip Monsters are always refining and manipulating architectures and instruction sets as we process to smaller and more powerful chips. Five or so years ago we had squeezed the chip real estate to its limit so the Chip Monsters had to look to other technologies to cram more transistors onto silicon.

Intel introduced double-mask double-etch lithography to carve circuit patterns on silicon wafers. AMD is advancing the immersion lithography process with their 45nm microprocessors.

As Intel decreased in size from 65nm to 45nm the number of transistors increased by 40% from 291 million to 410 million. At 45nm Intel introduced the 'high-K metal gate' (HkMG) transistors. They are simple 'switches' and the 'high-K' allowed these switches to be moved closer together without 'leaking' on their neighbor.

At 90nm an AMD Athlon 64 X2 processor had 243 million transistors (up from 164 million transistors on its single core counterpart). At 65nm the X2 Athlon has 221 million transistors. The Phenom has roughly 463 million transistors.

At 45nm AMD migration will introduce a new generation 'strained silicon' to increase their switching speed and power-efficiency. Then it becomes decision time. Subsequent 'spins' at 45nm will allow the possible use of what AMD calls 'ultra-low-k' gates or HkMG.

As I understand it, that decision rests with how quickly AMD wants to process to 32nm. They may skip HkMG at 45nm. The end of last year the 'Fishkill Partners' introduced HkMG at 32nm.
July 12, 2008 8:43:43 PM

Not quite...

Wisecracker said:
Intel introduced double-mask double-etch lithography to carve circuit patterns on silicon wafers. AMD is advancing the immersion lithography process with their 45nm microprocessors.


Intel had exactly one layer which was double patterned on 65nm. Double patterning is not only expensive (more tools to buy) but it's costly in terms of design, as the design tends to get locked in before manufacturing realizes a need for double patterning.

AMD is not "advancing immersion lithography" in the sense that they are *using* immersion litho to get the area scaling they need. When they were developing their design rules, they felt that they needed immersion to facilitate 45nm, where intel did not. So, yes, AMD gets to be the early adopter of immersion litho. It's a blessing and a curse.

What you also are forgetting is because AMD used the immersion card at 45nm, they will also struggle with a significant amount double patterning at 32nm. As of last February, the industry has no good solution to implement double patterning. The litho tools are not ready. The resists are not ready. The EDA tools are not ready.

Other companies (like intel) then get the tool advances benefit of seeing AMD struggle with immersion (and later double patterning) related defects.

Wisecracker said:

As Intel decreased in size from 65nm to 45nm the number of transistors increased by 40% from 291 million to 410 million. At 45nm Intel introduced the 'high-K metal gate' (HkMG) transistors. They are simple 'switches' and the 'high-K' allowed these switches to be moved closer together without 'leaking' on their neighbor.


You've got your dimensions wrong here. The 45nm node means area scaling. No matter how you do it. HiK does not buy you the ability to get your pitch down, per se. What HiK buys you is the ability to have a "thicker" gate oxide to prevent gate leakage (electron tunneling) at the same switching speeds. It does nothing to prevent channel leakage or other leakage mechanisms.

What this means is that if AMD does not introduct a HiKMG scheme, they will not be able to shrink the gate oxide along with the area scaling and will either have significantly higher TDP due to gate leakage or significantly lower performing transistors.

Wisecracker said:

At 90nm an AMD Athlon 64 X2 processor had 243 million transistors (up from 164 million transistors on its single core counterpart). At 65nm the X2 Athlon has 221 million transistors. The Phenom has roughly 463 million transistors.

At 45nm AMD migration will introduce a new generation 'strained silicon' to increase their switching speed and power-efficiency. Then it becomes decision time. Subsequent 'spins' at 45nm will allow the possible use of what AMD calls 'ultra-low-k' gates or HkMG.


Oy. there is no such thing as ultra-low-K gates. That would suck beyond belief. The ultra-lowK you are referring to is in the backend (metal layers) where you want to reduce the capacitance between metal lines.

IBM has announced a working HiK transistor using a gate first approach, where the metal gate is patterned at the poly step. Intel does it gate last, where polysilicon gates are made first, and then later removed and filled back up with metal. The first is more elegant, but can suffer from annealing/metal mobility problems.

July 12, 2008 9:01:49 PM

bobwya said:
Hi,

The Core 2 has an "out-of-order execution" model of instruction issue. Instructions can be issued continously as long as they are not dependent on the result of previous instructions, branching instructions have advanced speculative execution (effectively guessing whether to branch or not). The C2D architecture also is Superscalar in a similar way to the K8/K10 issuing batches of microinstructions each clock. In order for out-of-order execution to work microinstruction state changes must be commited in-order a technique that was being researched in the 1990's (a buffer is used to store changes until they can be safely committed, was called a "Future File" in academic papers).

So the real killer for AMD is that the C2D archiecture is chomping away on multiple instructions almost every clock while the K8/K10 architecture will be pay for load cache misses, etc. and will really heavily on Compiler optimization to issue 3-4 microinstructions per clock.

Bob


Actually OoO execution dates back to Penium days. All recent AMD CPU (K8/K10) has OoO capability.
July 12, 2008 10:05:51 PM

donkeywash said:
I know that Core 2's are alot faster than X2's; however, does anybody know why? From a technical perspective why can't AMD compete with the performance?

It depends on the type of application. Intel has a design targeting single threaded applications. AMD is targeting multithreaded applications. Using single threaded applications Intel is better. Start another application and check performance for the same applications that went very fast running alone, and that don’t run as fast anymore. Testing the same application on AMD and it will keep speed better.
AMD is also focusing on reducing latency when data travels to the processor. Intel has focused to have data IN the processor. Starting applications e.t.c is faster on AMD. Running applications that don’t use a lot of memory is faster on Intel.
July 12, 2008 10:53:15 PM

Seriously kassler... drop it. You still haven't proved how Intel's CPU perform less in multi-threaded environment.
July 13, 2008 12:35:03 AM

yomamafor1 said:
Seriously kassler... drop it. You still haven't proved how Intel's CPU perform less in multi-threaded environment.

Yes I have but you are allergic to everything that say anything good about AMD and you also think servers is computer made on another planet.
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July 13, 2008 1:01:53 AM

^ On Monday I shall show you (if I'm bored enough)

yomamafor1 said:
Actually OoO execution dates back to Penium days. All recent AMD CPU (K8/K10) has OoO capability.


hmm... Intel Atom is in-order however...
July 13, 2008 1:09:13 AM

kassler said:
It depends on the type of application. Intel has a design targeting single threaded applications. AMD is targeting multithreaded applications. Using single threaded applications Intel is better. Start another application and check performance for the same applications that went very fast running alone, and that don’t run as fast anymore. Testing the same application on AMD and it will keep speed better.
AMD is also focusing on reducing latency when data travels to the processor. Intel has focused to have data IN the processor. Starting applications e.t.c is faster on AMD. Running applications that don’t use a lot of memory is faster on Intel.


The problem people are having with your analysis is that you are confusing the CPU architecture (that which does the acutal calculation) with the Memory controller.

You are absolutely correct, those programs which need a lot of memroy bandwidth will perform better on the AMD systems. That's why spec_fp_rate is a favorite benchmark for AMD. AMD also has a significatnly better x87 FPU than the Intel. Unfortunately, a lot of FP operations are NOT done using x87, but rather with SSE. So AMD wins with scientific software, less so with others.

What's keeping AMD in the game is that, as you pointed out in your last response, it's the server space (particularly 4-node and above) which requires memory throughput more than raw horsepower. There's enough CPUs wanting enough data that intel is bus limited, while AMD is not. In the 2-socket space, intel's raw speed in enough to keep it ahead. Longer to access memory, process the data faster. Single socket? No comparison.

The problem AMD has is that, barring a very few programs, NOTHING on the desktop can saturate intel's bandwidth.

Looking to *why* intel's are faster.. people have already pointed it out. More instructions per clock on the C2D architecture. And a faster clock. It's that simple. Rather, it's complex, since I can't tell you *how* they did it, only that they *did* do it. Others can give you the architectural reasons -- I'm just a process guy. You look to single-threaded benchmarks to get the data for that, and there, it's all intel, all the time. Even on FPU.

Be careful about latency -- AMD is certainly getting the raw data to the CPU die faster, but once there, their latencies of cache actually increased going from 90 to 65nm. Unintended, of course, but it's there. AMD would be wise to figure out how to optimize the cache as well as intel has done. (and intel would be -- no wait -- is wise to copy the on-die-memory controller.)
July 13, 2008 5:52:15 AM

kassler said:
Yes I have but you are allergic to everything that say anything good about AMD and you also think servers is computer made on another planet.


Apparently you're also allergic to anything that proves Intel CPU is not bogged down by FSB.

I've actually said a lot of good things about AMD. I really like their current GPU and chipset lineups, and their CPU really shines in 4P+ servers. However, anything below 4P servers, HPC, and few 2P servers, Intel demonstrates better performance / money and performance / watt.

I just think you've blown this "FSB" issue way out of proportion.
July 13, 2008 5:57:19 AM

amdfangirl said:
hmm... Intel Atom is in-order however...


That's because OoO execution demands a lot of computing power, and subsequently more die size from the processor.

You can take a look at a comparison between Core 2's OoO and K10's OoO.
http://www.realworldtech.com/page.cfm?ArticleID=RWT0516...

Such complex design is not really practical on Atom, as it will result in high power consumption and high heat dissipation. On the other hand, most handheld device programs are written in order to begin with, since most of the processors used (ARM architecture) do not feature OoO execution units. AFAIK, with the exception of Atom and Itanium, all Intel CPUs have OoO scheduling and execution capability.
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July 13, 2008 7:56:48 AM

^ And yet the VIA Isah is OoO and still retains the same thermal evolpe of the C7
July 13, 2008 8:44:31 AM

amdfangirl said:
^ And yet the VIA Isah is OoO and still retains the same thermal evolpe of the C7


...when C7 is built on 90nm, and Isaiah is built on 65nm.
July 13, 2008 8:47:21 AM

AMDzone < TheInq < Fudzilla

Watch out for Abinstine. He's full of it (this guy tried to argue that C2D was an inefficient design because the die size is larger per core). The best you can do is listen to Scientia. Although still a fanboy, he's the one with the most logical sense among the brood.
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July 13, 2008 8:56:25 AM

yomamafor1 said:
...when C7 is built on 90nm, and Isaiah is built on 65nm.


You win congrats!

Still, its a nice and efficient...
July 13, 2008 6:41:13 PM

donkeywash said:
I know that Core 2's are alot faster than X2's; however, does anybody know why?


Because Intel has an R&D budget thats worth more than all of AMD...
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July 13, 2008 8:03:40 PM

kassler said:
Here is one interesting thread
http://www.amdzone.com/phpbb3/viewtopic.php?f=52&t=1353...


Did you seriously just quote a AMD fansite? I mean seriously what the hell man?

Oh and you are obviously the guy named "gosh" since you talk the same BS there as you do here.

Oh and just to test out this little "theory" of yours I ran Winrar 2 times. It was on a 170MB file. I unpacked it while doing nothing once and it took 3 seconds (wow on an Intel machine too). Then I ran a game. Audiosurf (had it just running through the level of a random song and then ran Winrar again on the same size file. Guess wht? 3 seconds again. So considering that it should have slowd down since I started to run another program then why did it take the same time?

Seriously man. Just stop the BS.
!