How big is a DDR2 memory burst?

The memory timings you see (e.g. 5-5-5-18) relate to the latency, i.e. how long from when the request is first made, to when data actually appears on the bus.

The one thing I've never seen mentioned is how big a data burst happens, once the data starts moving. Oddly, the only system I do know that detail for is the PS2: it uses a Rambus system, where each burst is 8 quadwords, a quadword being 128 bits.

So does anyone know how much data is transferred after the CAS (and other) latency has been satisfied? An obvious guess would be enough to fill a cache line in the outermost (highest numbered) cache, but TBH I don't know that value for either Intel or AMD current architectures.

Thanks in advance for any thoughts,
J.