Wolfdale 6MB vs Yorkfield 12MB L2 Cache

I know this is comparing Apples with Oranges but I'll give it a shot to see if this makes any sense.

I have an E8500 at the moment running very nice and stable @ 4ghz (1.3 vCore) with good temperatures.

I don't need any sort of upgrade at the moment but this is purely planning for the future as I'm sure games (which is what I'm interested in) will become more multi-threaded with time.

Although Nehalem is just around the corner with it's new architecture and multi-core goodness, it doesn't really make a lot of difference to interger performance and doesn't have the traditional large L2 of Core2 CPU which games heavily derive their performance from (use of more than 2 cores in games isn't fully realised yet).

Add in the fact that only a few months ago, I shelled out a small fortune to get an nVidia 790i Ultra chipset....I'm not too keen to give up on Socet 775 yet ;)

Somewhere down the line, I'm looking to get a minor upgrade "on the cheap" by sticking a 45nm quad core in my 775 socket with a goal (hopefully!) of getting the clock speed to 4ghz like my currently dual-core setup (I know this'll be harder....I'm hoping the Q9550 E0 stepping will fit this bill!).

So my rather very long winded (still with me?!) question is.....

If an application that only uses one or two logical cores (i.e. isn't harnessing the power of all 4 cores), does the full 12MB L2 cache get used (i.e. all 12MB is available to each core) to give an advantage over the 6MB L2 cache of the Wolfdales, or would only half the cache (6MB) be available to the 2 cores actually in use? (as this generation of quad cores is actually 2 dual cores strapped together with each pair of cores having 6MB available to them)

Many thanks in advance for any help! :)
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  1. From what I've read Nehalem will be native 2, 4 or 8 cores Hyperthreaded so 4, 8 or 16 threads with L1, 2 and 3 cache with L1 and 2 being dedicated to one core and L3 being shared by all. Yorkfield has a dedicated L1 cache per core and a unified L2 cache so all cores have access.
  2. i think 6mb is shared between 2 cores, cause isn't a c2q just a 2 c2d's slapped together?

    and if you really wanted to, you could wait till the q9650 drops in price maybe later this year hopefully? its the only guarantee of getting an E0 stepping, and a awesome 9x multi... you can hit 4.0ghz with it easy with some nice air cooling, or watercooling which is what ill be settling for
  3. If memory serves, no, a CPU on one die cannot access any of the L2 cache on the other die in the package; it is limited to the L2 cache on its own die... It shares the cache with only a single other CPU. As a result, in 1- or 2-threaded applications, I don't think you'd see any improvement in performance at all. Coupled with the added difficulty of getting your clock rate back up to 4.0GHz there, and the simple fact that you'd be paying extra money, I think that staying with your WolfDale E8500 would be the best solution until the Nehalem chips come out.
  4. ^Umm... then why does all the quad core product say shared L2 cache?
  5. Grimmy said:
    ^Umm... then why does all the quad core product say shared L2 cache?

    Because as I understand, it IS, just not entirely; each die has its own 6 MB L2 cache, and that's fully shared between the two CPUs on that die, as I know. However, while CPUs #0 and #1 can use L2 cache #0, they cannot use L2 cache #1, which is available for CPUs #2 and #3. Similar to how the L1 caches can't be used by any core but the one they are assigned to. As I understand, some of this has been re-worked for Nehalem to allow much more cross-usage.
  6. So... Core 0 could not share its cache with Core 3?? :cry:
  7. That's what the FSB is there for.
  8. nottheking said:
    Because as I understand, it IS, just not entirely; each die has its own 6 MB L2 cache, and that's fully shared between the two CPUs on that die, as I know. However, while CPUs #0 and #1 can use L2 cache #0, they cannot use L2 cache #1, which is available for CPUs #2 and #3. Similar to how the L1 caches can't be used by any core but the one they are assigned to. As I understand, some of this has been re-worked for Nehalem to allow much more cross-usage.


    This is how I understand it too....I think the 12MB assumption is based on all 4 cores being used at the same time (which is rarely the case). I think this would mean single threaded apps are limited to 6MB cache.

    I'm not thinking of moving any time soon but I think I might get a E0 stepping quad core to use in conjunction with my high-end air cooling and hopefully get 4ghz when the next gen CPUs are released and the current gen comes down in price (assuming the next gen doesn't make a huge leap for gaming!)
  9. modtech said:
    That's what the FSB is there for.


    What do you mean by this mod....that the FSB allows access to the other 6MB cache for single threaded apps?

    Wouldn't this be a lot slower?
  10. Core 2 Quad Q6600: Four Cores for the Masses?

    That's basically it. (edit: which follows the same principle as the wolfdales being glued together as yorkies)

    And I guess my Humor is abit dry. :cry:
  11. No the other 6MB of cache won't be accessible for single threaded apps.
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