Comp won't start with New RAM

I've recently bought some new RAM for my computer but when I installed it the comp wouldn't start up. I have tried taking my old memory out and only using the new ones but it still won't start up.

New RAM: Samsung 2 X 2GB PC2 5300/5400 AM2 667MHZ DDR2 DIMM

Motherboard: GIGABYTE GA-MA69VM-S2

I have tried to only put one of the new memory sticks in with out any others in to see if it would work and it still wouldn't...I have tried them in all 4 slots.

I contacted the seller I got them from and he said that they are compatible and sent me out a replacement but they still won't work...any ideas?
12 answers Last reply
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  1. Can you get into the BIOS?

    If you can... adjust the Voltage and Latency to specs
  2. Can't get into BIOS- It won't start up.
  3. Does the mobo accept 2GB sticks?
  4. Supports: "4 DDR2 DIMM memory slots (supports up to 16GB memory)" Doesn't says anything about not supporting 2GB sticks eitherway but I presume it would.
  5. I just saw that you posted the mobo model. I agree with you on that. I can't find any mention of your RAM on Google.

    One thing you might try is to clear the CMOS on the mobo. I've never had to do that, but stranger things have happened.

    All RAM brands are not compatible with all mobos, even when they have the exact same specs.

    If the old RAM works and the new RAM doesn't then it may be incompatible.

    One way to eliminate that question, which usually isn't a problem, is to get RAM that is on the Qualified Vendor List.
  6. I do see a Samsung 2GB stick listed on that document:

    2GB Samsung M378T5663AZ3-CE6 DS Samsung K4T1G084QA-ZCE6

    On my ram (chips) is written: K4T1G044QA-ZCE7

    Close enough right?
  7. Those are different numbers, so they are different RAM. You can't make any judgments about how similar they are without more information from Samsung. Maybe you should email them.

    You are going to have to email Gigabyte. The only hit I got on your RAM is this one Whe there is DDR2 memory for Amd AM2 only - Forums. It's only the OP and he doesn't look to happy either, but at least it booted.

    I have to reiterate, if it works with the old RAM and not the new RAM, then it's probably the RAM. I don't know what it cost you, but you may need to cut your losses and get some other RAM, preferably not off ebay.
  8. May be you had solved the problem.
    I will help you to understand, because I have it too:

    K4T1G044QA-ZCE7 is a true DDR2-800 chipset, as said by ...E7 last chars.
    Some vendors sell memory modules populated by K4T1G044QA-ZCE6, a DDR2-667 chipset (see ...E6 last chars)
    as DDR2-800.
    Then, we have a overclocked DDR2-667 chipset, not a true DDR2-800 chipset.

    BIOS recognizes your K4T1G044QA-ZCE7.
    (In Gigabyte MOBO´s, after entering BIOS Setup,
    enter CTRL F1, as said in first menu screen, to see hidden menu items.

    Open menu item "Advanced Chipset Features" and you will see timings for the installed memory module.

    But, if all is here, why it doesn´t work?

    Well, DDR2-800 chipset must have a 400 MHz clock
    (the ending ..2 in DDR2 means => 2 times the base clock frequency)

    Intel processors use a Front Side Bus (FSB) chipset ( Intel 965, VIA P4M900, etc).

    This chipset synchronizes the clock frequency for all FSB devices.
    In my case, I have a MOBO Gigabyte GA-VM900M, VIA P4M900 FSB chipset,
    with a Intel E2180 CPU, FSB 800, running at 2000 MHz = 10X the base clock at 200MHz.
    (Gigabyte CDROM software DMIView show this, try it).

    If E2180 sets clock at 200 MHz, to achieve 2000 MHz (by multiplying it by 10 times),
    how can I get the needed frequency (400 MHz) to run DDR2-800 chipset?

    DDR2 only doubles frequency, not quadruplicates it ( 800 = 4 x 200).

    That is: some mobo design synchronizes CPU and memory modules,
    making it impossible to setup BIOS to any memory chipset in market.

    1) DDR2 Memory Tutorial at
    2) Understanding RAM Timings at
    3) Memory Overclocking at
    4) Tight Timings vs High Clock Frequencies : Introduction at,1236.html
    where is said:
    ".... We picked an AMD Athlon ... 64 system
    for our detailed memory performance analysis, because the memory controller
    is part of the processor and is thus sensitive to memory speed and timing changes...."

    AMD eliminated FSB chipset. Instead, AMD processors control memory chipset directly.
    The old compatibility between Intel and AMD motherboards finished.

    As said, K4T1G044QA-ZCE7 works fine in mobo's designed for AMD Technology,
    but not in Intel FSB chipsets. May be this market feature determined its actual low price.

    The first target in assembling some CPU with some arbitrary memory chipset, is:
    how to make a stable, fine tunned working pair (CPU, Memory)?

    This only can be achieved by:
    (1) de-synchronizing the two clocks;
    (2) fixing the setup for one and adjusting the other to it.

    As explainned in the cited paper, not all motherboards permit option (1) be selected.

    Then, our choice must be option (2): we must adjust memory timings to CPU already given clock.

    Each memory chipset has a maximum speed, that is,
    a it cann't deliver a data bit before, say, 15 ns (nanoseconds).

    If CPU clock setup frequency is very high,
    then memory chipset is "shorted" and cann't execute all designed tasks to deliver a data bit.

    On the other side, each memory chipset has a maximum interval of time to retain
    the fetched data bit.
    After this time, say 75 ns (nanoseconds), the data bit is lost and cann't be delivered to CPU.

    If CPU clock setup frequency is very low,
    memory chipset cann't do its work, because it is losting fetched bits.

    In the first case, when CPU clock setup frequency is very high,
    we must "enlarge the time" in the memory side, giving more clock steps to memory chipset, from 3 steps to 4 or 5 steps.

    In the second case, when CPU clock setup frequency is very low
    (memory chipset is waiting and is losting its fetched data bits),
    we must "shrink the time" in the memory side, and get these data bits as soon as possible,
    that is, reducing the memory chipset clock counts, from 5 steps to 4 or 3 steps.

    To do that, we must work with the "auto" parameters got by BIOS, and
    adjust them according to the situation found in our (CPU, Memory) pair.

    In my case, my CPU clock (200 MHz) is very slow for a DDR2-800 chipset (400 MHz).
    Then, i must change "auto" found 5T to 4T, may be 3T.

    The target is to change defaults 5-5-5-15 to "short timings" 4-4-4-12
    where the series means

    (CL)-(tRCD)-(tRP)-( tRAS = CL + tRCD + tRP )

    "Advanced Chipset Features"

    [Auto By SPD] ==> [Manual]

    SDRAM CAS Latency (CL) DDRII 5 ==> 4
    Bank Interleave 8 Bank ==> Disabled (No Interleave)
    Precharge to Active (tRP) 5T ==> 4T
    Active to Precharge (tRAS) 15T ==> 12T
    Active to CMD (tRCD) 5T ==> 4T
    REF to ACT/REF (tRFC) 42T/43T ==> 38T/39T
    AcT(0) to ACT(1) (tRRD) 3T ==> 3T

    My Windows Server 2003 R2 (32 bits) is working well.
    The target is Linux Fedora 9 - 64 bits, which presented problems with default (auto) setup.
  9. As was willing to know a AMD mobo, I downloaded the manual of
    your ga-ma69vm from

    and what I saw?

    In the first diagram:
    CPU CLK+/-(200 MHz)

    Well, may be you have a low clock problem:
    How get 800 MHz from 200Mhz?
    Try lower clock cycles for memory 4-4-4-12 or 3-3-3-9
  10. Sorry, these texts:
    "Well, DDR2-800 chipset must have a 400 MHz clock "
    "how can I get the needed frequency (400 MHz) to run DDR2-800 chipset? "

    "DDR2 only doubles frequency, not quadruplicates it ( 800 = 4 x 200). "

    are wrong, DDR2-800 has a 200 MHz base clock .
    The number "...800..." isn't a clock, but a "Data transfers per second"
  11. Running Fedora 9 Memory test on my GA-VM900M, I had:
    1) only first 256M are OK!.
    2) OS using less 256M runs fine.

    Conclusion: problem isn't clock timings, but design.
    K4T (1G) 044QA-ZCE7 is a 1 GigaBit chip (256M x4 x2 module)

    May be some FSB chipset have no support for 1 GigaBit chip.

    In relation to Intel 965 FSB Chipset:
    this is true:
    800MHz 1Gb technology not supported)

    Certainly, the same for my VIA P4M900 and your AMD 690 FSB Chipsets.
  12. Finally, problem solved!

    A link in
    Thaiphoon Burner - SPD and EPP editor

    helped me to found the true parameters for K4T1G044QA-ZCE7.

    Manual timings must be:
    6-6-6-18 Refresh tRFC = 51 T at 400 MHz clock

    As Gigabyte GA-VM900M BIOS(F6) allows 5T max, the only possible settings:

    5-5-5-18 Refresh tRFC = 70 T

    work fine ( Fedora 9 MemTest86+ all tests passed OK).

    Sorry, I used "so many bytes" from database, trying to say all I was getting on the road, while searching for a solution.
    I am very grateful, this software (free downloaded from Showshock Softnology Website)
    helped me a lot.

    Below, the complete report of Thaiphoon Burner, showing all EEPROM SPD of the memory module.

    Manufacturing Description
    DRAM Manufacturer: Undefined
    Module Manufacturing Location: 0
    Module Part Number: Undefined
    Module Manufacturing Date: Undefined
    Module Serial Number: 00000000h
    Module Revision Code: 00 (00h)

    Legitimate Architectures
    Fundamental Memory Type: DDR2 SDRAM
    Module Type: UDIMM (133.35 mm)
    Module Nominal Height: 30 mm
    DRAM Package: Planar
    Number of Ranks: 1
    Number of Banks on SDRAM Device: 8
    Module Rank Density: 2 GB
    SDRAM Device Width: 8 bits
    Number of Row Addresses: 14 bits
    Number of Column Addresses: 11 bits
    Module Data Width: 64 bits
    Error Checking SDRAM Width: N/A
    Data Error Correctrion Code: Not supported
    Data Parity: Not supported
    Refresh Rate: Reduced (7.8 us)
    Voltage Interface Level: SSTL 1.8 V
    Number of PLLs on the DIMM: 1
    Module FET Switch External Enable: Not included
    Analysis probe installed: Not included

    DRAM Timing Parameters
    Burst Lengths Supported: 4, 8
    CAS# Latencies Supported (tCL): 4T, 5T, 6T
    SDRAM Access time from Clock (tAC): 0.40 ns
    Maximum Device Cycle Time at any CL (tCK max): 8.00 ns
    Minimum Clock Cycle Time (tCK min): 2.50 ns
    Minimum Clock Cycle Time at CL X-1: 3.00 ns
    Maximum Data Access Time from Clock at CL X-1 0.45 ns
    Minimum Clock Cycle Time at CL X-2: 3.75 ns
    Maximum Data Access Time from Clock at CL X-2 0.50 ns
    Minimum Row Precharge Delay Time (tRP): 15.00 ns
    Minimum Row Active to Row Active Delay (tRRD): 7.50 ns
    Minimum RAS# to CAS# Delay Time (tRCD): 15.00 ns
    Minimum Active to Precharge Delay Time (tRAS): 45.00 ns
    Minimum Write Recovery Time (tWR): 15.00 ns
    Minimum Write to Read CMD Delay (tWTR): 7.50 ns
    Minimum Read to Precharge CMD Delay (tRTP): 7.50 ns
    Minimum Act to Act/Refresh Delay Time (tRC): 60.00 ns
    Minimum Refresh Recovery Delay Time (tRFC): 127.00 ns
    Address and CMD Setup Time Before Clock (tIS): 0.17 ns
    Address and CMD Hold Time After Clock (tIH): 0.25 ns
    Data Input Setup Time Before Strobe (tDS): 0.05 ns
    Data Input Hold Time After Strobe (tDH): 0.12 ns
    Max skew between DQS and all DQ signals (tDQSQ): 0.20 ns
    Max Read Data Hold Skew Factor (tQHS): 0.30 ns
    PLL Relock Time: Undefined

    Thermal Parameters

    * DRAM Case Temperature Rise from Ambient

    DT0: due to Activate-Precharge 6.30 °C
    DT2N/DT2Q: due to Precharge/Quiet Standby 6.40 °C
    DT2P: due to Precharge Power-Down 0.645 °C
    DT3N: due to Active Standby 6.90 °C
    DT3Pfast: due to Active Power-Down with Fast PDN Exit 3.65 °C
    DT3Pslow: due to Active Power-Down with Slow PDN Exit 0.825 °C
    DT4R/DT4R4W: due to Page Open Burst Read 15.60 °C
    DT5B: due to Burst Refresh 18.50 °C
    DT7: due to Bank Interleave Reads with Auto-Precharge 27.00 °C

    * PLL Case Temperature Rise from Ambient

    DT PLL Active: due to PLL Active Not supported

    * Register Case Temperature Rise from Ambient

    DT Register Active: due to Register Active Not supported

    * Thermal Resistance

    Psi[T-A DRAM]: DRAM Package from Top (Case) to Ambient 48.0 °C/W
    Psi[T-A PLL]: PLL Package from Top (Case) to Ambient Not defined
    Psi[T-A REG]: Register Package from Top (Case) to Ambien Not defined

    * DRAM Maximum Case Temperature

    TCaseMax 95 °C

    * Thermal Requirements

    DT4R4W Delta 2.80 °C
    DRAM High Temperature Self-Refresh Entry Supported
    Double Refresh Rate at DRAM TCaseMax > 85°C Required

    SPD Protocol
    SPD Revision: 1.2
    SPD Bytes Used: 128
    SPD Bytes Total: 8
    SPD Checksum: 9Ch

    Summary Specification
    RAM Classification: PC2-6400 (DDR2-800)
    Module Capacity: 2048 MB
    Frequency tCL tRCD tRP tRAS tRC tRFC tRRD tWR tWTR tRTP
    400 MHz 6.0 6 6 18 24 51 3 6 3 3
    333 MHz 5.0 5 5 15 20 43 3 5 3 3
    267 MHz 4.0 4 4 12 16 34 2 4 2 2
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