Nehalem memory limitiations?!?!

[chunkymonster]

Been perusing the various sites for any Nehalem related news as i am very interested in this beast...a 4GHz overclock on air...Intel's first major foray into an IMC...new chipset...official SLI support...new toys to play with...WOOHOO!

Whilst surfing I came across these two articles over at Fudzilla. I know, I know, take Fuad with a grain of salt.

Nehalem to only support DDR3 800 or 1066
and
Nehalem doesn’t like more than 1.65V

So, my questions to those in the know...
1) Will only supporting DDR3-800 or DDR3-1066 place any limits on bandwidth?
2) Is 800 and 1066 "fast enough"?
3) Will a v-max of 1.65 inhibit higher than 4GHz overclocks?
4) Is 1.65v a "design by-product" in the Core i7 uArch or a max voltage limitation of the 45nm node?
5) Is this a genuine limiting factor of Nehalem or effectively a non-issue?

I was a bit surprised to read this as I thought that Nehalem would let the DDR3 beast out of its cage. I was guessing that Nehalem would be introduced on the market with starting out with at least DDR3-1333. But then again, if understand things correctly, the Core2 uArch isn't really limited by DDR2-800, let alone DDR3-800 and up.

Thoughts? Comments? Informed opinions greatly appreciated. Thanks!

 

[alvine]

interesting, I will wait for 32nm cpus anyways......I'm waiting for my boxes with parts to come :[

 

[yomamafor1]

Intel does indeed semi-confirm that the highest DDR3 speed for Nehalem will be DDR3 1066. However Vcore and VRAM are completely different, handled by two different sets of regulators. Therefore I don't know what Fuddo was smoking when he wrote that.

As for the memory limitations, a single DDR3 1066 offers 8.5Gb/s of bandwidth. Multiply that by three....well, you get the picture. In short, memory bottleneck will not be a problem for Nehalem. QPI itself offers 25.6 Gb/s of bandwidth, per link.

EDIT: If you also add interleaved mode into the mix, you get (8.5Gb/s x2 (interleaved))x3 (tri-channel) = 51Gb/s.

 

[jimmysmitty]

^I agree with yomama. It seems a little too far fetched that the CPU will be limited by the VRAM voltage. And considering that DDR3 needs much less voltage to attain stable operation I would doubt it will limit the OC.

 

[cal8949]

that doesnt make sense tho when toms di the nehalem review they said there test system was ddr3 1600mhz

unless intel found out nehalems were running unstable with ram
http://www.tomshardware.com/news/intel-nehalem-core,5854.html
Processor Intel Nehalem 2.93 GHz
Motherboard Prototype X58 motherboard
Memory Crucial Ballistix DDR3-1600 1GBx2
Storage Seagate SATAII 750GB (ST3750330AS/P)
Graphics ATI Radeon 4850 HD
OS Microsoft Windows Vista Windows XP Era Ends SP1
Resolution 1280 x 1024
Patches hotfix_vista32-64_dd_ccc_hd4800series_64906

 

[zenmaster]

Garbage.
The Link above clearly shows the CPU running at a little over 0.8v

No way the DDR3 RAM is running at that voltage.
Sorry, Fudzilla is a failure again.

 

[Guest]

isn't the highest ddr3 ram somewhere low like 1066 or 1333? and then the rest is just highly oced?

lke ddr2... the highest jedec standard is 800 mhz while the rest of the levels are just overclocked versions...

so of course they would say they support the jedec...

 

[chunkymonster]

Intel does indeed semi-confirm that the highest DDR3 speed for Nehalem will be DDR3 1066. However Vcore and VRAM are completely different, handled by two different sets of regulators. Therefore I don't know what Fuddo was smoking when he wrote that.

As for the memory limitations, a single DDR3 1066 offers 8.5Gb/s of bandwidth. Multiply that by three....well, you get the picture. In short, memory bottleneck will not be a problem for Nehalem. QPI itself offers 25.6 Gb/s of bandwidth, per link.

EDIT: If you also add interleaved mode into the mix, you get (8.5Gb/s x2 (interleaved))x3 (tri-channel) = 51Gb/s.

One of the other tidbits in the Fudzilla article was that Vcore and Vram need be synchronous. Historically these two were independent of each other, but if true then 1.65v is the max for both Vcore and Vram; which would exclude the use of higher speed DDR3. Anyone have any insight into why Nehalem would require synchronous Vcore and Vram? Or am i interpreting it incorrectly?

Ah yes, tri-channel...was wondering why Intel chose this option rather than dual or quad channel memory...maybe they figured out early on that tri-channel was plenty enough.

 

[jimmysmitty]

^Well it adds a nice boost of memory bandwidth. But the server chips are getting Quad channel DDR3 and the low end desktops will have dual channel DDR3.

The only thing I think that would cause this is for the "Turbo Mode" self OCing and thats it. But if you disable that it should allow them to be independant.

But I still think its wrong because current 45nm CPUs stock voltage for 3GHz is about 1.15v and there is no way that DDR3 1066 that needs 1.65v for stability can run at 1.15v stable. And there is no way a 45nm CPU can run at 1.65v without extreme cooling like LN2.

So with that, This has to just be BS really because there are too many factors that do not add up.

 

[Crashman]

1) Will only supporting DDR3-800 or DDR3-1066 place any limits on bandwidth?
2) Is 800 and 1066 "fast enough"?
3) Will a v-max of 1.65 inhibit higher than 4GHz overclocks?
4) Is 1.65v a "design by-product" in the Core i7 uArch or a max voltage limitation of the 45nm node?
5) Is this a genuine limiting factor of Nehalem or effectively a non-issue?

1) Intel announced a while back that it was working on adding 1333 support, though its not clear if this will apply to all models based on this architecture.
2) DDR3-800 triple-channel has the same bandwidth as DDR3-1200 dual-channel, which is very good. DDR3-1066 triple-channel has the same bandwidth as DDR3-1600 dual-channel.
3) This is probably the I/O voltage for the memory controller. It has nothing to do with other parts of the chip. Aeneon already carries 1.50V DDR3-1600, so its just a matter of giving other companies time to catch up.
4) No
5) The only issue here is that most "performance" RAM is made of slower parts rated at a huge factory overclock. The Aeneon RAM I mentioned earlier is theoretically higher quality since it doesn't require overclocking techniques, but that same Aeneon RAM can't withstand the extra voltage needed to overclock it much further (you won't see it used in DDR3-2000, etc).

 

[jimmysmitty]

No whats interesting is some ppl don't seem to realize that now memory wont affect the OCing just like how a AMD CPU doesn't get affeced by the memory. The memory is no longer linked to a FSB but a IMC.

And considering that tripple channel DDR3 1066 has shown more than 2x the bandwidth of dual channel DDR3 1066 I am suprised anyone would complain at all.

 

[JAYDEEJOHN]

Yeah, from what Im getting, change that 133 clock, add a lil voltage if needed, and thats where your oc will come from, not thru the memory. The FSB limatations are no longer a concern with a IMC, especially one using DDR3, with all its BW. Its the internal clock at 133 that really is the ticket for better ocing. Ive heard it as high as 140s, higher 140s, and maybe a 150+ here and there

 

[jimmysmitty]

^I have seen 200 but the voltage they had was quite high so I don't know how plausable that would be. We have to wait and see once THG and Anand have a chance to show what their tinkering has given them. It is possible that all the Bloomfield based models will have a unlocked multi, with the EE having a higher unlocked multi. So say the EE will have up to 35 multi and the others will have up to 30 or something.

Of course that would be a dream and probably not possible but one can dream right?

 

[JAYDEEJOHN]

Sounds high, but sometimes dreams come true. Yea, an unlocked multi on anything other than a EE would be nice, even if it started at 2.4

 

[Reynod]

Considering the added complexity of a trichannel memory controller I would think it used a considerable amount of beffering circuitry to reduce impedence loading on the three sticks, and I would therefore not be surprised that the voltage of associated componentry locked to the cpu ... as a simple means of preventing instability. Voltage regulation would be paramount to keep signal noise at the memory controller to a minimum.

Remember the early A64's (in 939?? I can't remember well though) that didn't like multiple sticks ... same demon.

 

[JAYDEEJOHN]

Thats essentually what Ive heard as well.. Just because your memory can run at 2 volts, you better not run everything at that voltage. Ive heard that if you first boot with lower voltage memory, then pull it out and go to the higher, itll adapt, or something like that. Its so different, until we hear enough tweaks from the daring, who knows all of them?

 

[Reynod]

I must admit my fairly cursory analysis of Nehalem from Anand's articles leads me to believe that it is an excellent design .. .especially the modular approach.

Alas we are heading into economic mayhem ... which will most likely stall new technology.

Still ... the current 45nm stock is very good - more than good enough for gaming.

I bet Intel do in fact shrink the current 45nm quads to the next node too ... It would make good sense given that Nehalem requires a much more complex and expensive board layout.

Shrinking the current Yorky's and ussing the curent layout would be very cost effective.

Given the economic uncertainty this would be welcomed with open arms by the mobo manufacturers - who must be worried at the production expense.

I'd be interested what other's think of my view there ??

TC ... use one of your freebees eh ?? he heh ... constructively tho ..

 

[JAYDEEJOHN]

"Fastest" yes, as in timings, other than that, it wont matter that much

 

[jimmysmitty]

Hmmm, well, correct me I am wrong. Doesnt IMC like the fastest rated RAM available? BTW the IMC feature was given, as stated after, it's a lot more complex then that.

And AMD cpu not affected by memory? You mean the L2 cache on the cpu? If that's not what you mean then what are you smoking? LOL!

You know, back two years ago when Intel mentioned an "improved" netburst "like" arch with IMC, I thought it would never happen. But with the low fsb and high multiplier, it's starting to look that way. Especially, with hyperthreading making it's way back. LOL! I'll be damned, they weren't joking after all...

Yes a IMC does like the fastest memory available. But what I mean is that when OCing a AMD CPU the memory no long affects it. While with current Intel CPUs (C2D/Q) onces you hit a certain bus and depending on the quality of RAM you may need higher speed RAM to be able to OC to a stable OC. Since there is no more FSB with Nehalemthen the memory will not affect the chips OCing ability.

As for your last sentance, you are wrong. Nehalem is not Netburst based. It is Core 2 based still which is Pentium Pro/III based.

 

[JAYDEEJOHN]

Umm, using your previous statement and clarification, I said " "Fastest" yes, as in timings, other than that, it wont matter that much " , so tell me, how much did DDR2 improve AMDs chips? For that matter, we wont really see much of a boost from i7's DDR3, no matter how fast it is. I was pointing out that the biggest boost was from low latency, not overall speed, but you do get some from it.


I see what youre saying in that Intels netburst was HT+high multis, and thats where i7 is heading as well. Id guess its stages for Intel

 

[Stupido]

ddr3 is hella expensive

so lets hope the i7 will bring prices down...

 

[Crashman]

I was pointing out that the biggest boost was from low latency, not overall speed, but you do get some from it.

DDR3-1600 CAS7 should always outperform DDR2-800 CAS4, because it has lower latency. "Should Always" is dependant upon other components such as the memory controller however.

I'm here to smack people up the side of their head with the explanation if they can't figure out why 1600 C7 is less latency than 800 C4.

 

[JAYDEEJOHN]

Yeah, 8 is more than 7, nuff said

 

[BadTrip]

good to see you posting again Crashman.

+1

 

[JAYDEEJOHN]

Ive never had a reason to doubt crashman, ever.