Nehalem memory limitiations?!?!

interesting, I will wait for 32nm cpus anyways......I'm waiting for my boxes with parts to come :[

^I agree with yomama. It seems a little too far fetched that the CPU will be limited by the VRAM voltage. And considering that DDR3 needs much less voltage to attain stable operation I would doubt it will limit the OC.

Garbage.
The Link above clearly shows the CPU running at a little over 0.8v

No way the DDR3 RAM is running at that voltage.
Sorry, Fudzilla is a failure again.

One of the other tidbits in the Fudzilla article was that Vcore and Vram need be synchronous. Historically these two were independent of each other, but if true then 1.65v is the max for both Vcore and Vram; which would exclude the use of higher speed DDR3. Anyone have any insight into why Nehalem would require synchronous Vcore and Vram? Or am i interpreting it incorrectly?

Ah yes, tri-channel...was wondering why Intel chose this option rather than dual or quad channel memory...maybe they figured out early on that tri-channel was plenty enough.

1) Intel announced a while back that it was working on adding 1333 support, though its not clear if this will apply to all models based on this architecture.
2) DDR3-800 triple-channel has the same bandwidth as DDR3-1200 dual-channel, which is very good. DDR3-1066 triple-channel has the same bandwidth as DDR3-1600 dual-channel.
3) This is probably the I/O voltage for the memory controller. It has nothing to do with other parts of the chip. Aeneon already carries 1.50V DDR3-1600, so its just a matter of giving other companies time to catch up.
4) No
5) The only issue here is that most "performance" RAM is made of slower parts rated at a huge factory overclock. The Aeneon RAM I mentioned earlier is theoretically higher quality since it doesn't require overclocking techniques, but that same Aeneon RAM can't withstand the extra voltage needed to overclock it much further (you won't see it used in DDR3-2000, etc).

No whats interesting is some ppl don't seem to realize that now memory wont affect the OCing just like how a AMD CPU doesn't get affeced by the memory. The memory is no longer linked to a FSB but a IMC.

And considering that tripple channel DDR3 1066 has shown more than 2x the bandwidth of dual channel DDR3 1066 I am suprised anyone would complain at all.

^I have seen 200 but the voltage they had was quite high so I don't know how plausable that would be. We have to wait and see once THG and Anand have a chance to show what their tinkering has given them. It is possible that all the Bloomfield based models will have a unlocked multi, with the EE having a higher unlocked multi. So say the EE will have up to 35 multi and the others will have up to 30 or something.

Of course that would be a dream and probably not possible but one can dream right?

Considering the added complexity of a trichannel memory controller I would think it used a considerable amount of beffering circuitry to reduce impedence loading on the three sticks, and I would therefore not be surprised that the voltage of associated componentry locked to the cpu ... as a simple means of preventing instability. Voltage regulation would be paramount to keep signal noise at the memory controller to a minimum.

Remember the early A64's (in 939?? I can't remember well though) that didn't like multiple sticks ... same demon.

I must admit my fairly cursory analysis of Nehalem from Anand's articles leads me to believe that it is an excellent design .. .especially the modular approach.

Alas we are heading into economic mayhem ... which will most likely stall new technology.

Still ... the current 45nm stock is very good - more than good enough for gaming.

I bet Intel do in fact shrink the current 45nm quads to the next node too ... It would make good sense given that Nehalem requires a much more complex and expensive board layout.

Shrinking the current Yorky's and ussing the curent layout would be very cost effective.

Given the economic uncertainty this would be welcomed with open arms by the mobo manufacturers - who must be worried at the production expense.

I'd be interested what other's think of my view there ??

TC ... use one of your freebees eh ?? he heh ... constructively tho ..

"Fastest" yes, as in timings, other than that, it wont matter that much

I am? Where did I say that the Nehalem was based on the netburst? I put the quotes there for a reason. Hyper threading wasn't part of the feature set for netburst? Hmmm, low fsb and high multiplier until later on the fsb scaled wasn't netburst characteristics? Which is probably going to happen for i7. I'm seeing a pattern here that's simlar. Hmmm, If I do recall, those were all part of the feature set of netburst. Besides, the p3 is a p4 with a better clock per cycle and is more efficient. In general, that's basically the main difference. The reason why the p4 didn't make it, it because they didn't think the would run into the problems they did. Heat, inefficiency, throttling, etc. Let's make it more interesting, and nehalem seemingly want to scale with it's fsb mostly. 133 fsb to start with <---- oc capable anyone?

And did I mention I used quoted words in there? "Like" and "improved", Oh okay, just double checking cause evidently I didn't use them. And if you want to break it down to specific arch, what I said was a lot more accurate then you think. Besides, I said that Intel mentioned it, not me.

Jaydee, really? interesting... So... Why did AMD move to ddr2 or ddr3 then? From what your saying, ddr1 would slaughter ddr2 and ddr3 no matter how high they scaled then right? Rated speed does matter just to make it easier. You need both.

Comp keeps freezing, had to go back to this stupid computer.

I'll keep it short. At lower speeds below ddr2 800, AMD took a performance hit from ddr1. Now, with higher speeds, it was corrected and started seeing gains. Again, you need both. Seems though with ddr3 with high timings, speed was the winner after all. Also, with ddr3 and triple channel, it feeds the bandwidth that the i7 is probably going to need. Starts off with quad core.

Also, with ddr3, triple channel, and IMC, it should fit the i7 feature set nicely. I think they wanted to start with a low playing field obviously. ddr3 is hella expensive.

DDR3-1600 CAS7 should always outperform DDR2-800 CAS4, because it has lower latency. "Should Always" is dependant upon other components such as the memory controller however.

I'm here to smack people up the side of their head with the explanation if they can't figure out why 1600 C7 is less latency than 800 C4.

good to see you posting again Crashman.

+1

Ive never had a reason to doubt crashman, ever.

Problem is, i7 wont be BW limited at all, not because of DDR2 or DDR, but because its now running an IMC, which elimanates most of the BW problems from the get go, then adding DDR3 in tri channel, forget about it, but, if the cas is lower, its still moving faster as it is also wider, so its not really the DDR3 as much as the IMC, and the cas helps it move faster.

Get ready for the SMACK: I changed how much of the text was in RED.

My calculator says that DDR3-1600 (800MHz) cycles in 1.25ns, while DDR3-800 (400MHz) cycles in 2.50ns. Do the math, for DDR3-1600 C8 and DDR2-800 C4:
8 cycles at 1.25ns is 10ns.
4 cycles at 2.50ns is 10ns.
The point here is easy: DDR3-1600 C8 has the same latency time as DDR2-800 C4.

Oh, but you forgot about TIME. You kept thinking cycles, and ignoring that each cycle took HALF THE TIME. That just means the memory has proportionally higher latency...in proportion to its higher speed. It still has the same latency time.

But time is what matters here. If you have a game stutter for a fraction of a second using DDR2 and get fragged...then have the same-length stutter occur using DDR3, you get fragged the same way. You can't claim that the stutter was "worse" with DDR3 simply because the DDR3 was clocked higher.

LOL! I knew you would react like that, I'm not surprised. BTW, I didn't jump to conclusions. I did it in the form of a question. Oh, and it gets better, read more.

Like I said, the numbers do not refer correctly. Thus conufusion begins. I did say that. Did you start from the beginning when you read the comment? But... moving on. THE POINT IS, since you missed it like, damn, I won't go and read how many times I said this, NOT THE CAS! You smacked yourself trying to smack everybody else. Yeah, that's good, you know a lot about memory timing and cas. *Claps

LOL! You only proved my point, where did I try to explain cas in detail? Nowhere, you know why? YOUR ON THE WRONG PAGE! LOL! And no, I'm not whatever you want to say I am. And second, yes, are you still sure about that comment? I asked cause your comment was pointless! Taking what I said and further explaining that to make it look better. Yeah... Ummm, thanks? Ehhhh, no thank you.

The memory scaled, case and point, he was trying to make it out like the speed wasn't a big deal. I said, you need both. Either way, my point of it scaling with higher speeds still stands. And yes, it is still unique because of it bandwidth capabilities. I remember reading that ddr2 would phase out fairly quick, and it did, cause of ddr3.

BTW, thanks for another side comment and info, again... Stop smacking the **** out yourself for no reason. That's never a good reason.

You keep trying to be my side kick or something, it's flattering, but come on. I'm just trying to learn here.

This ain't 2006, I've seen how you posted back then. Very rude when it comes to memory details. Try dodging that one. Yeah, your the only one that's forgetting here...

Getting back to the subject. I should have just said, "Intel probably wanted to start at low playing field, and two ddr3 is hella expensive. Given the IMC, triple channel and the low fsb, it's probably going to be enough. Also, the voltage limit is cause JEDEC said so. Thank you." Lol.

Oh while your at it secretary, ummm, can you calculate for me the possibilities of the i7 scaling? With the high multiplier and low fsb, there's a lot of possibilities here. Thank you. *throws work on the desk

What's with the name calling? LOL! I must have hit a nerve with the defense mechanism there. You like to flame noob posts, and when you can't, well you got away with it this long didn't you? You were flaming noobs back then. What's with that? Just cause someone didnt spend their whole lives figuring out cas?

And I figured you would skip the middle. I ain't going to explain myself again. But one thing strikes me as weird... Where did I "forget" anything?

The only main comment I made was that cas was not everything in terms of performance. I said it needed both, which is true. The ddr3 you mentioned should outperform because it's just faster period, in ALL aspects.

I don't like people that try to get their little points across on one thing. See, that's how confusion starts. You forgot to mention that ddr3 is just faster in ALL ways. How could you leave such a misleading and incomplete comment? Now, I ask again, are you sure about that comment? Now that you look like the biggest noob flamer and definitely showed the time and error in this? This is what I didn't want to put out.

CAS latency and related timings will always affect how fast you read from memory.

RAM is like a book. CAS latency is how long it takes to open the book to the right page. RAM speed (e.g., the "1066" in DDR2-1066) affects how fast you read pages from the book.

Dual-channel means you can read from two books at the same time. Usually the books have to be the same size, and depending on interleave settings they may only be open to the same page at once.

An IMC bypasses the middleman MCH when recalling pages from memory. With an MCH, the page you need is sent to a central hub, which then opens the RAM to that page. It's like adding extra CAS latency, but that central hub might have its own caching. Additionally, the communication link with that central hub may not be fast or open enough to read RAM at full speed.

I would expect, with three books being read directly at once, the i7 platform may not be under much pressure to increase DRAM speeds. However, because the middleman is taken out, CAS latency should have a greater effect than it does on MCH platforms - like we see on Athlon64, but to a lesser extent because i7 has the cache sizes of Conroe/Penryn.

That's a good start, and the rest of the POST was great, but there's still the problem of how you're measuring "how long it takes to open the book to the right page". You see, the traditional argument is that DDR3 takes longer to open a page than DDR2. It doesn't. It takes more cycles, but because the cycles are faster, it takest the same time:

DDR3-1600 C8: 10ns
DDR2-800 C4: 10ns
DDR-400 C2: 10ns
PC-100 C1: 10ns

So, no matter how great your explanation is, it has to be "complete enough" to end this silly debate about memory getting "slower" in response time. It's disappointing that response times have stayed constant while data rates have gone up, but its not as bad as posters who only look at cycles...and not cycle times...would have us believe.

We're on the same page. The confusion probably stems from when a new RAM generation is introduced. Starting latencies, in real clock time, tend to be looser than those of the previous generation. And that point is hammered in with those release-date benchmarks blaming the lack of better performance on poorer latencies. That gets corrected over time, but no one does much in-depth benchmarking on yesterday's hardware.

As it is, the top timings for DDR3 right now approximate mainstream DDR2. However, Intel has warned us not to run our DDR3 at too high a voltage. That may mean we won't ever get to see high-end latencies, the ones where we run DDR2 at 2.0-2.4V (the latter with active cooling). So there is some merit to the complaint that DDR3 latencies are high. If anything, they've stagnated, and we're not used to stagnation in the tech world.

WR, niiiice. That's where I was getting at. He's showing his time and error BIG time. And Crashman, LOL! that was pity not agreement.


No, see, that's why I said, the point is not the cas, it's that everything else makes a difference. That was my first sentence. And the second sentence I wrote was about the numbers do not refer correctly. I was agreeing with what I said still. Where did you make this **** up? And, you must have been referring to yourself with the posted garbage, cause there was no error about anyone saying anything about cas. It was still misleading and incomplete. Even WR explained that everything makes a difference. And nowhere did I try to mislead a noob with posts. I stick with what I said. And really? What about Intel? They didn't take the performance hit as hard as AMD did... Again, your only focusing on your one thing. Well, let's ignore or fail to mention that twice the speed and twice the bandwidth, and being able to deliver that bw at high speeds has nothing to do with this. And lastly, don't smack yourself for this one.

"Disadvantages compared to DDR2
Commonly higher CAS latency
Currently (as of 2008) costs much more than equivalent DDR2 memory"

"DDR3 latencies are numerically higher because the clock cycles by which they are measured are shorter; the actual time interval is generally equal to or lower than DDR2 latencies."

And no, you can't complain about getting fragged, cause the technology of ddr3 will way more then make up for just one stupid aspect, that's why. Your were still only looking at ddr3's best scenario in cas. And it's sad, when people look at only cas, reminds me of the AMD fanboy troll days. And what's also sad is, that wasn't even the point and they miss it. Just like some people...

So... What really makes the difference? Oh yeah, we forgot about all the rest of the features that ddr3 has to offer. But technology doesn't advance and innovate, that's non sense.

Wr, yeah, I was going to mention the large caches being used until misleading posts hit the forum. See, what got me is that, I wonder where Intel's strength is going to be now. Due to nehalem having all the good features it'll be interesting to see how well this platform scales and performs later on. Although, the benchmarks we've seen so far aren't too impressive, but we can't be sure of that either.

So, cause I proved you wrong I'm the liar? I was saying that to wr, whether or not it was agreeing or being sarcastic towards his statements. It doesn't matter. You also assumed what I was reffering to. He didn't say that the technology was different? He didn't say that everything plays a factor in there? It just further supported that you gave out false and misleading information. I'm done with this troll.

Hey spud! Hey, could you even follow that conversation?