Well, I think this just may be another case of the AM2/65nm Fanboy BS.
Some people expected far more from AM2 and AMD 65nm than AMD delivered. That wasnt AMDs fault. AMD delivered what they said they would, but people were dissapointed because fantards had hyped AM2 and 65nm so much that they had those people conviced that both AM2 and AMD 65nm were going to be the second coming of Athlon 64.
In the case of i7, aside from that one kiddies blog that linked to some obscure site that said 'a confidential intel paper said 57thousand% gain in gaming" ((but failed to provide any proof of said document)), I havent seen anthing from Intel stating huge gains in gaming. The fanboys.....well thats a different deal...some were expecting another Core 2 jump.
Now, If anyone has anthing LEGITIMATE from Intel claiming huge gains in gaming, please, by all means, post evidence/links. Otherwise, this seems to be a case of kiddies hyping a product, not the companies hype.
First, an ACTUAL release from Intel. NOT BillyBobBoingos blog and honey barbecue site (might just as well be quoting sharipoopoo)
http://www.intel.com/pressroom/archive/reference/whitepaper_Nehalem.pdf
Now, some actual Intel slides from an Anand artical dated MARCH of this year. Nowhere did Intel claim 56% in gaming, Just as AMD did not make the astrotarded claims some of our fanboys were promoting on AM2 or 65nm.
From Anandtech
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3264&p=2
Nehalem allows for 33% more micro-ops in flight compared to Penryn (128 micro-ops vs. 96 in Penryn), this increase was achieved by simply increasing the size of the re-order window and other such buffers throughout the pipeline.
With more micro-ops in flight, Nehalem can extract greater instruction level parallelism (ILP) as well as support an increase in micro-ops thanks to each core now handling micro-ops from two threads at once.
Despite the increase in ability to support more micro-ops in flight, there have been no significant changes to the decoder or front end of Nehalem. Nehalem is still fundamentally the same 4-issue design we saw introduced with the first Core 2 microprocessors.
Nehalem effectively includes the only remaining advantages AMD held over Intel with respect to memory performance and interconnect speed - you can expect a tremendous performance increase going from Penryn to Nehalem because of this. Intel is expecting memory accesses to be around twice the speed in Nehalem as they are in Penryn, which thanks to its aggressive prefetchers are already incredibly fast. If you think Intel's performance advantage is significant today, Nehalem should completely redefine your perspective - AMD needs its Bobcat and Bulldozer cores if it is going to want to compete.
No quotes from Intel here, from Hardware Secrets, but a good read about : Note the 60% gain in VIRTUALIZATION, not gaming
http://www.hardwaresecrets.com/article/535/1
Nehalem is the codename of the new Intel CPU with integrated memory controller that will reach the market next month and that will be called Core i7; this architecture will also be used on CPUs targeted to servers (Xeon) and, a few years from now, it will also be used on entry-level CPUs. CPUs based on this architecture will have an embedded memory controller supporting three DDR3 channels, three cache levels, the return of HyperThreading technology, a new external bus called QuickPath and more. In this tutorial we will explain what’s new on this architecture.
Below we summarized a list of Nehalem main features, and we will explain what they mean on next pages:
Based on Intel Core microarchitecture.
Two to eight cores.
Integrated DDR3 triple-channel memory controller.
Individual 256 KB L2 memory caches for each core.
8 MB L3 memory cache.
New SSE 4.2 instruction set (seven new instructions).
HyperThreading technology.
Turbo mode (auto overclocking).
Enhancements to the microarchitecture (support for macro-fusion under 64-bit mode, improved Loop Stream Detector, six dispatch ports, etc).
Enhancements on the prediction unit, with the addition of a second Branch Target Buffer (BTB).
A second 512-entry Translation Look-aside Buffer (TLB).
Optimized for unaligned SSE instructions.
Improved virtualization performance (60% improvement on round-trip virtualization latency compared to 65-nm Core 2 CPUs and 20% improvement compared to 45-nm Core 2 CPUs, according to Intel).
New QuickPath Interconnect external bus.
New power control unit.
45 nm manufacturing technology at launch, with future models at 32 nm (CPUs codenamed “Westmere”).
New socket with 1366 pins.
Heres a good one from back in March
http://www.betanews.com/article/Sixcore_Intel_processors_coming_this_year/1205790710
The first TPC benchmarks for the "tick" generation of Penryn architecture actually delivered a bit more performance than even independent observers were expecting. No explicit performance data or projections for Nehalem were released today, though the early word on the street is to plan not to use the word "astounding" too many times in one paragraph.
Maybe Intel did claim huge gains, but I havent seen a single legitmate copy of any such claim, so, 'Be the first to
proveIntel made the claim!!!'
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