http://download.intel.com/design/processor/specupdt/320836.pdf
so how bad is it????
Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS)
Invalidation
Section 10.9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS) of the
Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System
Programming Guide will be modified to include the presence of page table structure
caches, such as the page directory cache, which Intel processors implement. This
information is needed to aid operating systems in managing page table structure
invalidations properly.
so how bad is it????