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tbl on i7???

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a b à CPUs
December 1, 2008 12:54:26 PM

http://download.intel.com/design/processor/specupdt/320...

Quote:

Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS)
Invalidation
Section 10.9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS) of the
Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System
Programming Guide will be modified to include the presence of page table structure
caches, such as the page directory cache, which Intel processors implement. This
information is needed to aid operating systems in managing page table structure
invalidations properly.


so how bad is it????


More about : tbl

a b à CPUs
December 1, 2008 12:59:59 PM

http://www.fudzilla.com/index.php?option=com_content&ta...
Quote:
Here is the word to word quote: "In rare instances, improper TLB invalidation may result in unpredictable system behavior, such as system hangs or incorrect data. Developers of operating systems should take this documentation into account when designing TLB invalidation algorithms. For the processors affected, Intel has provided a recommended update to system and BIOS vendors to incorporate into their BIOS to resolve this issue."


Bit ironic, won't you say :?
something wierd with native quadcore desing that causes these problems, eh?
a b à CPUs
December 1, 2008 1:12:36 PM

Kari said:
http://www.fudzilla.com/index.php?option=com_content&ta...
Quote:
Here is the word to word quote: "In rare instances, improper TLB invalidation may result in unpredictable system behavior, such as system hangs or incorrect data. Developers of operating systems should take this documentation into account when designing TLB invalidation algorithms. For the processors affected, Intel has provided a recommended update to system and BIOS vendors to incorporate into their BIOS to resolve this issue."


Bit ironic, won't you say :?
something wierd with native quadcore desing that causes these problems, eh?


lol.....ya....

so did intel copy amd n unintensionally 4got to remov the tbl bug...

PS: plz don flame me. m jus wondering
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a b à CPUs
December 1, 2008 1:47:09 PM

yeah, the desing is so similar to AMDs, even the problems are the same. lol
December 1, 2008 1:52:52 PM

Yes, AMD and Intel both had problems with their TLBs, but the similarities end there. Intel can resolve their issues with a BIOS update while AMD had to fab an entirely new CPU. Im no CPU designer, but me thinks Intels issue is no where near as bad as AMDs.
a b à CPUs
December 1, 2008 2:02:12 PM

amd also had a bios fix, but it actually disabled the buffer. So it wasnt really that good of a fix...
a b à CPUs
December 1, 2008 3:34:33 PM

Yes, I wouldn't go praising Intel yet. They haven't said what there fix is. In both cases however the problem is extremely rare and won't effect most people. No matter what Intel's fix is it will probably hurt performance some (maybe not as much as AMD's) and it will probably be better not to use. Intel would be stupid if they didn't fix the issue in their next version/revision (which is all AMD did).
December 1, 2008 4:03:23 PM

I wasnt praising Intel, I was just saying that from everything Ive been able to read about Intels bug, it seems the BIOS "fix" will actually fix the problem with their TLB. Where as the AMD BIOS "fix", as Kari stated, simply disabled the TLB altogether. Only time will tell if thats truly the case.
December 1, 2008 7:28:00 PM

yes for most, but not in the server market
a b à CPUs
December 1, 2008 8:44:07 PM

blackened144 said:
Yes, AMD and Intel both had problems with their TLBs, but the similarities end there. Intel can resolve their issues with a BIOS update while AMD had to fab an entirely new CPU. Im no CPU designer, but me thinks Intels issue is no where near as bad as AMDs.


true. although it is still funny both companies fan into this problem :kaola:  i bet AMD had a little laugh at the expense of Intel on this one.
December 1, 2008 8:57:59 PM

rangers said:
yes for most, but not in the server market


I do kind of wonder if this will result in the Nehalem-based Xeons getting delayed. I suspect however that the problem will be fixed with the next stepping which should be ready before the Nehalem server platforms are available in 6 months or so.
a c 126 à CPUs
December 2, 2008 3:38:12 AM

Its not really a design copy, all CPUs have had a TLB system in the cache for quite a while.

But considering that its something that HAS been around I doubt its going to affect anyone.

And obviously it doesn't affect much since the CPUs are able to hit 3.2GHz+ without any errors thus far.
December 2, 2008 4:16:26 AM

jimmysmitty said:
Its not really a design copy, all CPUs have had a TLB system in the cache for quite a while.


TLBs are really nothing to do with the CPU cache; they're essentially a cache of the page table to make virtual address translation faster. Intel have had them since at least the 386.

Either way, the reason why it was a big story on Phenom was that it cost a 10% performance hit to fix, not because it had bugs per se; if it could have been fixed with a 0.1% performance hit, no-one would have cared other than rabid fanboys.
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