TheGreatGrapeApe posted this in another thread which made me curious as to the relationship between TSMC and ATi/Nvidia.
ATi can produce almost triple as many RV770 on single wafer and are also said to have a higher yield rate after that. The G200 is 2.25 times the size, and the RV770 can fit more in the high yield center and even in the spaces around the edges. I think the numbers are 228 : 86 per wafer right now, and the 55nm shrink should make it just under 120 raw G200b die per wafer (a 256bit memory interface might yield about 135/wafer), which still is a long way from the RV770 which would still be near the 2:1 ratio, especially if yields don't improve. Right now supposedly the yields are making it even worse and closer to 4:1 ratio, so they need to improve both dies per wafer and yield ontop of that.
Both ATI/AMD and Nvdia are fabless and relay on TSMC to manufacture all there video cards, what I can't understand is why does ATI get its cards produced on small dies then Nvidia? Why doesn't Nvidia just tell TSMC to produce it's card on the smaller technology?
The die is the area all their transistors take. ATi's architectural design of RV770 takes up a smaller area, therefore has a smaller die. And I assume that architectures need to be changed/altered/rearranged for a smaller process, and the GTX200's aren't ready for it.
Basically, the die is controlled by ATi/Nvidia because of architecture, the smaller technology doesn't make up for the difference, regardless, and Nvidia itself isn't ready for 55nm process.
TSMC produces what you send them. They don't design the chip, AMD and nV do. nV has a history of waiting for mature processes and not risking productionon new processes ever since the FX5800 let down. They've even gone so far as to call ATi's adoption of Low-K as 'dangerous'.
However the current buzz is that nV wants to get on the new processes quicker nowadays and so they will push hard into 40nm and may even be the first to launch their high end on 40nm not waiting for a mature mid-level part first.
The other thing is that ATi/AMD's been pretty agressive pushing past full nodes straight into half-node production, that was very radical for chip mfr which usually likes to mature the base model and then go to the optical shrink.
That's part of what's behind the choice of fab technique, but another major issue is transistor # and design, ATi has been more effective at using their surface area to it's maximum with less and less empty die space.
One thing I forgot about in the G200b calculations is whether or not nV decides to move the NVIO on-die like they did with the G80->G92 transition, that was about 50mil transistors that don't just slip into the empty spaces, so that might actually keep dies per wafer low even with a smaller memory bus. That the 230:90 numbers are with TMDS/RAMDAC/etc vs not is even more impressive really.
Supposedly the return rate on the RV770 is higher at the outter edges where defect/failure rates are usually higher.
But also remember essentially we're talking about a 1.4billion transistor G200 vs a 956million transistor RV770 so all things being equal the nV die would be bigger. The only way they would be equal would be if nV was the one more efficient with their space and that currently doesn't seem to be the case.
No, that's not it, TSMC comes up with the FAB, AMD and nV decide whether or not they want their design put on this one or that one.
There's advantages and disadvantages.
ATi going quickly to 55nm and skipping 65nm was a wise choice, but it's still a risk, ATi got hosed in the 80nm HS process that TSMC offered, there were lots of issues with yield and it didn't offer the high speeds they had hoped for.
That's the risk, do you try the new untested process on the chance it lets you put more dies on a wafer and maybe get higher speeds (or lower power consumption and temp) or do you buld on a more mature process that gives up those benefits, but might give you higher yield of good chips from those dies that are produced. Also older processes are usually cheaper by about 10% per wafer. And if you can have someone like UMC do the fab work too, then a more mature process gives you additional capacity, which may be already tight or spoken for at TSMC.
It's not a simple thing either to just pick a process, you don't just plonk down the same design on a different process unless you don't mind wasting space. Often a process shrink lets you add things in newly created spaces or re-arrange the transistors.