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Command rate or timings?

Last response: in Overclocking
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July 26, 2010 7:43:14 PM

which would be better?

5-5-5-15 @ 2t

or

6-6-6-18 @ 1t

More about : command rate timings

a b } Memory
a c 100 K Overclocking
July 26, 2010 8:01:09 PM

Ummm... my guess would be 5-5-5-15 2T, but honestly I don't know. Would be interesting to see someone look into it.
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a b } Memory
a b K Overclocking
July 27, 2010 4:19:22 PM

Also: http://www.tomshardware.com/forum/176007-30-dram-comman...

Quote:

When the MC (Memory Controller) first tries to access memory, it has to latch onto a memory bank, known as CS (Chip Select). Then it proceeds to find the column (CAS), the Row (RAS), and then return the data to the CPU. Now, 1T means it takes 1 clock cycle to "find" a memory bank, vs. 2T where it takes 2 clock cycles to "find" the memory bank. But there's a sorta quirk, this only happens the first time data is attempted to be fetched from memory, and all subsequent accesses to that chip are done w/o delay, making the command rate null after the initial chip fetch.

"Whether the chip select can be executed in a single clock or whether it needs two clocks, depends on a variety of factors. Among the most crucial contributing factors appears to be the number of banks populated within the system from which the correct bank has to be selected. In a single bank configuration, the system already knows that all data have to be within this bank. If more banks are populated, there is an additional decision involved. Translated, that means that the number of chips within the entire pool of system memory plays an important role in how fast the DRAM command can be executed. This is highly oversimplified but to spell it out, it means that a single DIMM with only 8 chips (single bank) is easier and faster decoded within the entire possible memory space than 2 DIMMs with 2 banks each.

Other factors involve the distance of the DIMM slot from the memory controller and, most importantly, the quality of the DIMM's PCB. If a 4-layer PCB with its relatively high noise level is used, there is a fat chance of ever hitting a 1t command rate. A 6 layer PCB on the other hand has a better signal to noise ratio and can greatly speed up the decoding (on the level of the PCB). It is, therefore, not surprising that, even if the same chips are used on different DIMMs, the differences in the PCB will dictate whether the module is able to perform at a command rate of 1T or 2T"


So in a nutshell, just with having to raise latencies such as CAS, RAS, etc. when overclocking to remain stable, you should raise the command rate as well. Now, I know that this may be old or may not of been needed, but I actually never knew and I know a few people on here didn't, if you find it helpful, good, if you didn't, well, something to read .
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a b } Memory
a b K Overclocking
July 27, 2010 4:24:04 PM

Found another one for you, too:

http://www.overclock.net/amd-memory/32605-1t-vs-2t-comm...


Quote:
The Bandwidth tools (Everest & SiSoft) show a significant difference between running 1T vs 2T Command Rate - upwards of 25%, however, the Benchmark tools did not reflect such a large gap and there seems to be about a 2-3% performance hit when running 2T. It would appear that the Bandwidth Tools use some test process which is not reflective of the real world situation and as a result people quote these figures as being the reason not to use 2T timing...

Now if you look across the DDR scale you will see that if you are able to increase DDR by 7-10% this will have effectively reclaimed the 2-3% performance hit of the 2T setting. This is something to consider when trying to get that high OC where maybe 2T is stable but 1T just isn't.
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a b } Memory
a c 100 K Overclocking
July 27, 2010 4:52:00 PM

Awesome info Scotteq. I did not know that much detail about it. I think tonight I'll set it to 2T and then see if I can hit better than CL8 at 1600mhz. I've had very little luck in lowering timings.
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