Block size is typically around 4kiB, but erase-blocks seem to be 128kiB to 512kiB.
4kiB blocks understandable, (although I don't see why an ECC couldn't span 8 512B blocks), but 128kiB is so large there must be some important design issues I don't know of.
My guesses are it's something along the lines of:
- erase voltage is so high that blocks require significant insulation from each other to avoid leakage.
- there's a large one-per-erase-block component that doesn't get much smaller if you reduce erase-block size.
But again, those are purely guesses to give an idea of what I'm looking for.
I'm not an expert in this, but I've always assumed that it was because erases are a very time-consuming operation. Including more cells in an erase operation would reduce the erase time-per-byte to manageable levels.
From what I can tell the substrate is only shared by the cells in a single block. Otherwise you'd have to erase an entire chip, which would not be very practical. My guess is that having the minimum erasable block equal to a single page would simply be far too complex and would push up the manufacturing cost.
I thought the substrate came as single piece and the whole chip was built onto & into it. But insulators can be laid onto it and I guess thick insulation layers could be used to separate blocks, if that's what's needed to isolate them.
Man I wish I finished my semiconductor courses. I'm actually slowly revising my physics so I can try again.