hi i have the same setup but 8Gbs of ram instead of 4 and they work fine... strange how they dont work with you... i changed the timmings to match the timmings they're rated for, but even before that, they worked fine... i dont think changing things in the bios well help yo much :S might be something with the ram.... try testing it on another machine or something... :s (btw they arent in the compatibility list but i assure you they work :S)
the problem is that when I look on the motherboard compatability list, the memory I purchased is not shown as compatible.
Does this mean the memory will simply not work?
Lots of memory that will work never makes the approved list - it's endemic to the industry. For GBs, what happens is the approved memory list is made up when the MOBO is introduced from sticks they have been provided samples of, and never updated thereafter; in addition, many of the memory manufacturers that you'll see there you've never heard of, as (and I've said this before) I'm sure you can pick them up at any gas station in Taiwan, but they're not to be had here. That's also why, for a lot of boards, there are scads of 512M and 1G sticks, but few 2x2s and 4x2s...
Overall - don't worry about it - do the "Load Optimized Defaults", and if it works OK - you're good!
I think You have diferent sticks... from your first info I assume that You have http://www.ocztechnology.com/products/memory/ocz_ddr3_p...
I have same Mobo and this sticks and i run them @ 7-6-6-24 with 1.9V
Anyway Ill join you with your question what are all that settings in BIOS, some of them arent even in manual.
For a quick rundown on 'what is all this stuff': http://forums.tweaktown.com/f69/memory-timings-explaine...
For a more comprehensive look, try "What Every Programmer Should Know About Memory" that I've placed here: http://www.mediafire.com/?dnhrjhrxgyw
It's long (114 pages!), but thorough; I'd suggest 'skimming' chapter one (the 'intro') for its 'gist'; chapter two is the 'real meat' - the physical operation... Three is more to understand CPU selection, as it describes cache, organization, 'snooping' and the like, and the rest (except for the last chapter, which is interesting in a 'scifi' sort of way, concerning possible new technologies on the horizon...), unless you're writing programs, can be ignored!
Only last 4 remains:
Bank interleaving (enabled)
Channel interleave (enabled)
DQS training control (Perform DQS)
CKE Power Down Mode (Disabled)
Memclock tri-stating (disabled) - I dont rly inderstand what this do
Googled all of them, but have found only theoretical info, no practical usage on MA790FXT-UD5P.
I dont rly inderstand what Memclock tri-stating do exactly... on my system i cant boot OS with "enabled".
Anyone have idea what is best setum of these 4? I use these settings ^
OK - I can't be particularly helpful here, at least from a firmly established hardware oriented basis - 'cause, as usual, it appears to be top-effing-secret! To start out, I spent nearly an hour casting around to try to get some documentation; searching AMD tech doc database turned up exactly one item for the 790FX chipset: http://support.amd.com/us/ChipsetMotherboard_TechDocs/A...
Read it and weep (literally!)! And then people criticize me for criticizing AMD and their lack of publicly available documentation, and likening the difference between Intel docs and AMD docs to, sort of, microns and light years!
Interleaving is, generally speaking, a good thing, and you want it happening whenever possible; I have been told that this idea has led me to a mistake in setting up AMD CPU/chipset combos with selectable DCTs Mode; I automatically assumed that 'ganged' (dual-channel) would be faster, due to interleaving - but, I have been told (but, unfortunately, not shown any numbers) that this is not always so... I would leave it enabled for both bank and channel... For a bit more technical treatment, you could give this a read: http://www.realworldtech.com/page.cfm?ArticleID=RWT1104...
It's a bit dated, but will give you the general idea...
As for DQS training, I found an old, old (had an AGP bus!) AMD doc that described a precursor to this, and, if they are at all like Intel, once they latch onto a design feature, my guess is they'll stick with it until it becomes totally obsolete - simply adapting the technology to faster and faster operation... The chipset contains programmable delay lines, that can be physically 'adjusted' to match RAM timing elements; these PDLs can be trained, to 'wobble', and observe the results, in order to more closely match the actual physical layout of the DIMMs, and the 'meander' of connection lines to them... The chipset can then be programmed to periodically ( like, every ten to the seventh, eighth, or ninth clock cycles) 're-train' their circuitry, but I could not figure out, from the available documentation, why this would be desirable; I also have to assume this 'disables' the memory circuitry for the amount of time it takes to 'wobble and home in on' these settings... I can't imagine that temperature would 'shift' the underlying impedances (loads) of the RAM access circuitry enough to make this necessary, and I don't know why else you'd do it... Short of trying it both ways, and running some 'synthetic' memory benchmarks at each setting, my advice here would be to disable...
CKE power down, I believe, will depend on which 'sleep state' you've enabled; if you're using an S1 sleep (power-on suspend), leave it disabled; if you intend to S3 (suspend to RAM), you probably want it enabled - again, best thing is to test - whether, and how quickly, you can 'wake up' a 'sleeping' machine; if you're like me, and leave all the 'green crap' turned off - won't matter!
Re 'tri-stating', the underlying idea is explained fairly clearly here: http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/CompO...
What it's doing on this board is anybody's guess - the only place I've ever heard of tri-stating a memory bus is on multi-processor server board, and it's pretty much been superceded by having each processor 'hooked up' to its own memory banking, and then 'hyper-transporting' blocks back and forth... I imagine this is in the top-secret, eyes-only, need-to-know basis, NDA-required, "once you read this, we have to sew your lips shut", AMD AGESA processor start-up documentation - I used to know somebody who had a copy, but I think he's in a prison camp on Titan!