I'm doing my own reading on the chipset, but I'm just trying to get a few hand-outs of information to help me comprehend it better.
Quote :
The northbridge typically handles communications between the CPU, RAM, AGP or PCI Express, and the southbridge.
If you can have a x64 FSB between the CPU and Northbridge, but smaller lanes
throughout the rest of the chipset, something must happen to the data when it's in the Northbridge. What happesns to it?
Also...
How does data travel through the chipset between the CPU and GPU when they both have different clockspeeds? Is the term 'clockspeed' only applicable to the outbound data speed for a processing unit?
If you can have a x64 FSB between the CPU and Northbridge, but smaller lanes
throughout the rest of the chipset, something must happen to the data when it's in the Northbridge. What happesns to it?
Also...
How does data travel through the chipset between the CPU and GPU when they both have different clockspeeds? Is the term 'clockspeed' only applicable to the outbound data speed for a processing unit?
These are both basically the same question.
The very high speed bus to the Northbridge is there for connectivity to the GPU or RAM sockets. Such high speeds aren't required when the data is passed through to the south bridge, since the devices connected to the south bridge are much slower.
When passing date from the CPU to the south bridge, or to a GPU with a different clock speed, the data is buffered in the North bridge. Think of it like people transferring from a bus to a subway - several buses come in and people accumulate on the subway platform, waiting for the next subway. The subway comes along, scoops them all up and empties the platform. Then the process repeats itself. The same thing works in reverse order.
Ah, I see. So the key here is that the data is buffered in the North Bridge before going out elsewhere.
I know that PCIe buses are more advanced and runs as a unidirectional serial bus rather than parallel like normal PCI buses do. I'm assuming that's the way the FSB runs is the same was as the PCIe, unidirectonal. Is this the case?
I think PCIe would be better described as full duplex rather than unidirectional, since data travels in both directions with dedicated signal lines for each direction.
The FSB is a bidirectional parallel bus that operates more like PCI than PCIe. It is most definitely NOT the same as PCI, but it is parallel, like PCI is.
"Lanes" is a term that's used with PCIe, not with other buses (at least that I've seen). When I say the FSB is parallel, what I mean is that a 64-bit set of data is transferred over 64 discrete connections, one direction at a time (along with addressing and control signals on their own dedicated connections). A particular bus cycle may transfer 64 bits of data from the CPU to the North bridge, and then the next bus cycle may transfer a different set of 64 bits in the other direction.
Actually it's more complicated than that because the FSB is pipelined, which means that each data transfer takes multiple clock cycles, but different stages of the transfer are done at the same time as other transfers by using different groups of signals.
It's not so much how the "electricity" works as how it's been harnessed. The generic term "Computer Architecture" kind of covers it all, but there's a *lot* of stuff that fits under that moniker.