PCIE 3 bottlenecks in 2011?

I intend to get a core i7 on an x58 with 2 pcie 2 x16 ports. The new NV gt 300's and ati 5000 series are going to be pcie 3- how much will these cards be bottlenecked by the pcie 2 spec?

Considering that PCI-E 1 is just now starting to bottleneck with multi-GPU cards, I wouldnt be too worried.

We're not there yet, but as more and more devices move from PCI->PCI-E (looking at sound cards/sound processing in particular...), you do stretch the limits of the bus...

I often wonder how much more bandwidth routing audio through a ATI card takes up...

http://www.engadget.com/2008/06/12 [...] s-surface/

Mactronix

What exactly are you meaning by that, simpleton that i am is confused.

Bandwidth won't be an issue for any of the above, especially not for a 2 card situation, even if they were 2 VPUs per card.

It would be best to implement PCIe 3.0 in a sideport type situation first where the larger bandwidth and low overhead would benefit inter-VPU communication, and they wouldn't have to rely on the finalization of the draft spec which still hasn't happened yet, as long as the output end of the bridge was PCIe 2.0 compliant.

In addition to Mactonix's info there's the official launch info from last year as well as the updated 3.0 FAQ;

http://www.pcisig.com/news_room/08_08_07/

http://www.pcisig.com/news_room/fa [...] _FINAL.pdf

In addition to what VH1 said, remember that HD Audio, USB 2.0 , Gigabit ethernet, and SATA controllers could all together be handled by a single lane of PCIe 2.0 like VIA's old V-link.

And really it's not the bus that's the limit it's the chipset, and it's limited by both the # of lanes it supports as well as it's ability to communicate quickly to/from the CPU and memory. As seen in most 1.1 vs 2.0 tests/reviews even the X2 cards aren't affected by a change of 1.1 to 2.0 so much as by a lane count restriction. Also you could have a chipset that supports 4 x 2 VPU cards each running full speed and 16 lanes internal and external, but then can CPU and memory handle that much of a workload across the chipset?