FSB Parity

[netburst]

Hi Guys was looking to upgrade my Pentium Dual Core procesot to a Core 2 Quad and i came across this feature in the CPU specs called FSB Parity. Anyone has any idea what it is and what it does?

 

[hefox]

http://en.wikipedia.org/wiki/Front-side_bus

 

[B-Unit]

I dont see the word Parity anywhere in that article. Way to go.

 

[sminlal]

Parity is a way of checking for errors. It makes sure that the data sent out by the CPU over the FSB are received correctly by the North Bridge, and vice versa.

Intel CPUs have had bus parity for several years now. It's a terrific feature, and complements all of the error checking done over other buses such as USB, SATA, networks, etc. IMHO the biggest glaring hole in the whole scheme is that in most desktop systems there is absolutely no error checking done for data stored in memory.

 

[BenShami]

I understood FSB parity as the matching of frequency between the FSB and Memory in order to maximize data flow without controllers seeking to clip bus or memory speed...a way of seeking parity. parity would be putting 1333mhz ddr2 on a 1333mhz bus, or with dual channel using 667mhz ddr2 in dual channel mode to fill the bus thus reaching full parity. non parity would be using ddr2 800 in dual channel mode to fill a 1333mhz bus. The memory controller would clip the frequency until it found something it could work with say 620 or less ... you can see what happens... you are lowering the theoretical threshold by using non parity memory. many motherboards and even some of the new core i 7 may work with such uneven multipliers but what does it do to overall performance?

 

[jimmysmitty]

I understood FSB parity as the matching of frequency between the FSB and Memory in order to maximize data flow without controllers seeking to clip bus or memory speed...a way of seeking parity. parity would be putting 1333mhz ddr2 on a 1333mhz bus, or with dual channel using 667mhz ddr2 in dual channel mode to fill the bus thus reaching full parity. non parity would be using ddr2 800 in dual channel mode to fill a 1333mhz bus. The memory controller would clip the frequency until it found something it could work with say 620 or less ... you can see what happens... you are lowering the theoretical threshold by using non parity memory. many motherboards and even some of the new core i 7 may work with such uneven multipliers but what does it do to overall performance?

This.

 

[sminlal]

I understood FSB parity as the matching of frequency between the FSB and Memory in order to maximize data flow without controllers seeking to clip bus or memory speed...a way of seeking parity.

No. You're thinking of a different meaning for the word "parity". The kind of speed matching you're referring to is called "buffering".

In usage for a computer bus (be it a front side bus, PCI, SCSI, etc.), parity is used for error correction, as described in this Wikipedia article.

As an example of the parity signals used on the bus, here's an excerpt from Section 5.1 of the Intel Xeon Processor 5000 Series Datasheet, describing the parity signals used to detect errors on the address bus:

AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]# signals. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high.

 

[BenShami]

ok...yeah... that makes sense... matching the error correction... ecc... non-ecc and buffering...maybe Im on the wrong forum then.. ill look for buffering.. thanks

 

[hacker_tosh]

so if you could buy the q9650 (which intell lists an non fsb parity) for the same price as the q0550(which intell lists as fsb parity)
would you chose the 9550 for the fsb parity feature over the 9650?

PARITY HARITY!

 

[sminlal]

As I mentioned in the other thread where you posed the same question - it depends on how concerned you are with data corruption. For example, most people don't bother with ECC memory even though it prevents memory errors that can go undetected in most desktop systems.