Tom's Hardware > Forum > CPU & Components > CPUs > Why AMD cpu does not support HyperThreading??

Why AMD cpu does not support HyperThreading??

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I am a AMD fanboy but ... Currently I am using a Intel i7 pc.

because of NO amd cpu support 8 Thread.
When a compiling a software with Visual Studio + Incredibuild
HyperThreading give a huge amount of performance boost.(50% bulidtime faster)

I'm wonder why amd do not support hyperthreading.
more Threading is critical for Grid Process(especially: Software compiling with Incredibuild)

maybee it's because of Intel's patent?? or
amd's architecture's drawback??


Is there are any Roadmap for AMD's multithreading support CPU??
I'm desire for AMD's 4Core/8H cpu.

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because Intel has a patent for SMT and AMD can't include CMT, of which they have the patent, for whatever reason.

Reply to Helloworld_98

Theres no AMD architecture drawback. In fact i7 is exactly like the original true 4 core phenom with integrated IMC. They were just able to implement it better and get more clock speed with the die shrink to 45nm.

Reply to zipzoomflyhigh

The cynic in me wants to think this must be the talking point of the week :lol:

Reply to wisecracker

I don't "think" it has anythng to do with patents, but rather the design of the chips them selves.

The Pentium IV (RIP) had hyperthreating (or SMP by another name) but the real word benefit was small to non-existant in anything other than a very small number of server applications.

The reason there was no real word gain was the PIV despite having a fabulously long 20 (or in Prescott 31) stage pipeline it could only actually retire 2 instructions per clock cycle, so no matter how full the pipeline was stuffed with instructions the absolute 2 instructions per clock cycyle barrier could never be broken.

The Nehalem design is different -it can retire 4 (and in some rare cases where there has been micro-op fusion) 5 instructions per clock cycle. It is quite rare for the Nehalem pipeline to be fully loaded so that a single thread has a full 4 instructions per cycle to retire, so there is extra room to run a seperate thread down the same core to use up some of the excess capacity to retire instructions.

The Phenom core is roughly in between the PIV and Nehalem - it can generally retire 3 instructions per clock cycle. (Intel and AMD use different micro-oops so a "direct" apples to apples comparison is a bit tricky) Because of this it does not have the same ability to actually do useful work on a second thread like Nehalem can, so AMD likely has not implemented the feature becuase it would do them very little good.

Reply to TheVorlon

^ Good explanation, Vorlon. Hadn't really considered it from that perspective, but it makes a load of sense. IIRC, SMT can gain anywhwere from slightly negative to +30% in performance, depending on the code being executed, at around 5% extra transistor budget.

Just as with 'native' vs. MCM, much of AMD's disparagement of SMT has more to do with marketing than the facts. And just as AMD's Magny Cours will be MCM, I suspect they will get around eventually to using hyperthreading as well, when they are able :).

------------------------------ jennyh wrote: AMD break-even Q4 2009. *Gauranteed* - And she's probably right! :D
Reply to fazers_on_stun

It has nothing to do with patents because Intel patented Hyper-threading, not SMT. SMT is nothing new either.

Reply to randomizer

because real men use real cores

http://www.techpowerup.com/?102445

------------------------------ "Envy is ignorance" - Henry Thoreau : Best quote ever.

http://www.pingtest.net/result/3022953.png
Reply to xaira
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