Pcie 2.0

[Alan Mostafavi]

would you please tell me the difference between PCIe2.0 x16 and PCIe2.0 x8 and also PCIe2.0 x4 and PCIe2.0 x1? please explain about all these pcie in detail and simple language. sincerely yours Alan

 

[badge]

http://www.directron.com/expressguide.html

 

[MRFS]

Also, much more technical detail is here:

http://en.wikipedia.org/wiki/PCI_Express


[begin excerpt]

PCI Express 2.0

PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007.[8]

The PCIe 2.0 standard doubles the per-lane throughput from the PCIe 1.0 standard's 250 MB/s to 500 MB/s.

This means a 32-lane PCI connector (x32) can support throughput up to 16 GB/s aggregate.

The PCIe 2.0 standard uses a base clock speed of 5.0 GHz, while the first version operates at 2.5 GHz.

PCIe 2.0 motherboard slots are backward compatible with PCIe v1.x.

PCIe 2.0 cards have good backward compatibility, new PCIe 2.0 graphics cards are compatible with PCIe 1.1 motherboards, meaning that they will run on them using the available bandwidth of PCI Express 1.1.

Overall, graphic cards or motherboards designed for v 2.0 will be able to work with the other being v 1.1 or v 1.0.

The PCI-SIG also said that PCIe 2.0 features improvements to the point-to-point data transfer protocol and its software architecture.[9]

In June 2007 Intel released the specification of the Intel P35 chipset which does not support PCIe 2.0 only PCIe 1.1.[10]

Some people may be confused by the P35 block diagram which states the Intel P35 has a PCIe x16 graphics link (8 GB/s) and 6 PCIe x1 links (500 MB/s each).[11]

For simple verification one can view the P965 block diagram which shows the same number of lanes and bandwidth but was released before PCIe 2.0 was finalized.

Intel's first PCIe 2.0 capable chipset was the X38 and boards began to ship from various vendors (Abit, Asus, Gigabyte) as of October 21, 2007.[12]

AMD started supporting PCIe 2.0 with its RD700 chipset series and nVidia started with the MCP72.[13]

The specification of the Intel P45 chipset includes PCIe 2.0.

[end excerpt]


MRFS

 

[MRFS]

> Some people may be confused by the P35 block diagram which states the Intel P35 has a PCIe x16 graphics link (8 GB/s) and 6 PCIe x1 links (500 MB/s each).[11]


An x1 PCI-E 1.0 lane is capable of 2.5 Gbps / 10 = 250 MB/second IN EACH DIRECTION,
so the aggregate bandwidth, taking both directions into account, is 500 MB/second.

SATA's serial protocol includes 1 start bit + 8 data bits + 1 stop bit = 10 bits per byte transmitted,
hence we divide the raw bandwidth in gigabits per second by 10 to get the equivalent number
of bytes transmitted per second.

(That should clarify the confusion caused by the P35 chipset diagrams.)

PCI-E Gen2 doubles that to 500 MB/sec. IN EACH DIRECTION
so the aggregate bandwidth, taking both directions into account, is 1 GB/sec
(500 MB/sec. in one direction + 500 MB/second in the other direction).


MRFS

 

[badge]

Yeah, I did not post the wiki link for op. I wanted to give a two word explanation of 'bandwidth available'. I went with the most simple link I could find.

OP wrote:

please explain about all these pcie in detail and simple language.

 

[MRFS]

You're right: the simplest solution is the best solution


MRFS