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Intel's L1 & L2 &L3 Cache

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September 8, 2009 8:16:59 AM

Hello

i know that Cpu cache is very usefull, Its the first thing that cpu search's before ram, and runs much faster than ram, and closer to the cpu to avoid latency.

what i wanna know is what do they mean by L1 Cache L2 Cache And L3 Cache, and whats the difference between them.

also, whats the reason of making smaller CPU's every 2 or 3 years, for example, Pentium Dual-Core used a 65nm, core i7 uses 45nm, whats the difference between them other than one is smaller than the other, and what benefits do they get.

Thanks in advance.

More about : intel cache

a b à CPUs
September 8, 2009 8:34:21 AM

L1 cache is the smallest and fastest. L2 is slower and larger, L3 is yet slower and larger. Also, in current designs, each core gets its own dedicated L1 and L2, but L3 is shared between all the cores.

As for the size? The CPUs aren't shrinking. In many cases, they're growing. The size you refer to is the size of an individual transistor within the CPU. The smaller each transistor is, the more of them will fit in your CPU, allowing for faster CPUs with more stuff crammed in. Smaller transistors also switch faster, allowing higher clock speeds, and use less power.
September 8, 2009 9:04:18 AM

cjl man your everywhere lol, thanks alot you answered about every question i asked in this forum +1rep

L1 Cache is the fastest Cache, each core has its own L1 cache its the smallest but its the fastest and the first one to accesses by the Core.

L2 Cache is slower than L1, L2 cache is the 2nd cache that the core search's for its data, and bigger than L1.

L3 Cache is shard between all of the cores, in the core i7 for example, is shared between all 4 cores, and bigger than both L1 and L2.

so basically what your saying is, Cpu first search's L1 cache, if a miss happens, then it goes to the bigger cache which is L2, if it don't find the data that is looking for there,then it goes to the bigger Cache which is L3 Which is Shared between all 4 cores.

so is L1 Cache faster because its smaller than l2 and l3 or is it faster because its the first cache the cpu looks into?


so 65 and 45 is inside of the CPU chip? lol i thought it was something els.

so the smaller it gets the better clock speed we get and the less power, ok i got that one.

please Correct me if my info isnt right.


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a b à CPUs
September 8, 2009 9:36:10 AM

It's faster because it is smaller and because of its proximity to the CPU core. The design of the cache is also different. L3 is also on a separate power and clock plane to the CPU cores - L1 and L2 run at the CPU clock speed, but L3 runs at a slower clock.

As for the 65 and 45, yes, those are the size of the elements inside of the chip itself. Here's a good way to show it:

The Pentium 4 "Northwood" chip had a die size of around 145 mm^2 (the physical size of the chip) with 55 million transistors at 130 nm.

The current i7 "Bloomfield" chip has a die size of 263 mm^2. It also contains 731 million transistors at 45nm. This means that a Bloomfield i7 is around 1.8 times larger than a Northwood Pentium 4, but contains 13.3 times the number of transistors. This is what the smaller number means - Bloomfield can pack 13.3 times the number of transistors into just 1.8 times the area with around double the power consumption. This allows for a far more complex and high performance chip without too much of an increase in power or size.
a b à CPUs
September 8, 2009 11:00:28 AM

L1 is the fastest because it runs at the same clock speed as the processor. It is really expensive to try to increase the L1 that is why it is always quite small.

My memory of computer architecture is quite hazy but I believe the L1 stores instructions, L2 and L3 stores data. (Could someone confirm this)
a b à CPUs
September 8, 2009 11:46:19 AM

There are 2 L1 caches actually - an L1 instruction cache, and an L1 data cache. Both are quite small.
a b à CPUs
September 8, 2009 4:03:19 PM

Here's a picture of the Nehalem microarchitecture. The L3 cache is shared among the 4 cores, but there are separate L2 and L1 caches for each core. The L1 instruction and data caches are at the top and bottom, and the L2/L3 caches are on the right.

Surda, with respect to your question in another thread about hyperthreading and the pipeline, you can see the execution units (adders, floating point units, etc.) near the bottom of this diagram in the grey box:

September 8, 2009 6:06:56 PM

L1 & L2 runs at the clocks speed

L3 runs at the QPI speed then i gusse, and can cache use QPI and get the data from ram insted of having the cpu it self doing that.

thanks sminal for this pic, it helps alot.



a b à CPUs
September 8, 2009 9:01:13 PM

wow. your are full of questions surda. lol. well it not a bad thing. The main way most people learn.
September 8, 2009 11:13:04 PM

lol im just trying to keep them busy thats all : P

well because im going to college next year, gonna go computer science next year, so im just trying to get help here.
a b à CPUs
September 8, 2009 11:14:53 PM

ah i see.
September 8, 2009 11:22:13 PM

Where I'm from, Computer Science is 90% software, and if you're trying to prepare for it, you should be working on your programming (both in general, and learning several languages).

You might know that and be doing that already, I just wanted to make you aware (as I know a couple people who wanted to study hardware and ended up studying software because they didn't do enough research).
a b à CPUs
September 9, 2009 2:42:49 PM

Well these questions would help him a lot on a computer architecture course. This is also a great way to visualize what is happening when assembly language is explained.

Though you might be more interested in computer engineering if you want to make chips more than software.
a b à CPUs
September 9, 2009 3:41:10 PM

Dekasav said:
Where I'm from, Computer Science is 90% software, and if you're trying to prepare for it, you should be working on your programming (both in general, and learning several languages).

You might know that and be doing that already, I just wanted to make you aware (as I know a couple people who wanted to study hardware and ended up studying software because they didn't do enough research).


I used to recruit computer engineers (hybrid between electrical engineers and CS) for my company - they were in great demand until the hiring freeze due to the economy. Also we paid a large hiring bonus to them, zilch for the CS candidates. So my recommendation is computer engineering if not electrical engineering with a minor or 2nd concurrent degree in CS. If somebody wants to maximize their hiring chances & starting salary..
September 9, 2009 3:59:00 PM

At my college, our computer engineers actually take all the courses necessary to have a minor in CS, all we have to do is make sure you apply for both the major and minor.
September 9, 2009 9:23:32 PM

i do know that CS is all about Software i already know alot about that, been reading about java and C++ and such for about a year, but i never knew anything about the hardware.

i was learning about these languages its too complicated but then you get to a point where you relize you know how this Software work, but you have no idea on how the hardware does all this for you in order to work on the software..

so i searched on google for hardware forums, found alot and got intrested in this one and here im askin alot of questions lol.

Although now im 50% - 50% dont know if i should go for computer science or computer engineer, and if i could get advice on that i'll be thankful.

which one gives better salary computer science or computer engineer?
September 10, 2009 5:42:16 PM

Don't decide based on salary, I know LOTS of people that try, and they end up unhappy (hopefully before they graduate, so they can change majors). Go for what you enjoy most. If you have a real affinity for calculus, high level math, and electronics, go engineer/hardware. If you can program well/enjoy programming, algorithm analysis, and such, go CS/software.

They do overlap a little, though, either way. Good programmers have an understanding of how hardware works and engineers need to know how software works in order to design hardware to better suit it.
Anonymous
a b à CPUs
March 20, 2010 8:29:39 PM

Hey Guys,

This was an awesome thread which got digressed in between.. I have been working on caches recently and I had a couple of doubts..

1. Block requests first reach L1. If L1 misses, it goes to L2 and if L2 misses, it goes to L3 - Right?

2. In Intel Nehelam, L2 is non-inclusive and L3 is inclusive of L1 and L2. Do you guys have any idea about what happens to a write request? Does that block get written into respective L3 block?

- A.

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