PAE is not special. PAE has been a part of x86 for many years. Since Windows 2000, PAE has been a part of Windows. The only reason why xp/vista/7 is not able to use more than 4GB is because Microsoft made it so.
And this is not really just a "Windows xp/vista/7"-discussion. The OP asked how you could break the 4GB barrier, because some people do, and I gave the reason. I know you dislike it, but it is the truth.
And how much a single application can use is irrelevant here. The question was how much ram the OS could use as a total.
"Farthermore, programs and drivers must be coded in such a way to make sure the proper page table is always accessed, otherwise you run into lots of memory errors. PAE is a workaround, not a solution."
Is technical not true. It is 100% false when talking about applications.
You have proven so many times (here and) in the past that you don't have much knowledge in how memory access/management works in x86, so give it a rest.
I am referring to the guy who found out that by patching just a few bytes in the vista kernel, you can remove the 4GB-limitation implemented by Microsoft.
There seems to be a lot of confusion in the industry about what's commonly called the Windows “4GB memory limit.” When talking about performance tuning and server sizing, people are quick to mention the fact that an application on a 32-bit Windows system can only access 4GB of memory. But what exactly does this mean?
By definition, a 32-bit processor uses 32 bits to refer to the location of each byte of memory. 2^32 = 4.2 billion, which means a memory address that's 32 bits long can only refer to 4.2 billion unique locations (i.e. 4 GB).
In the 32-bit Windows world, each application has its own “virtual” 4GB memory space. (This means that each application functions as if it has a flat 4GB of memory, and the system's memory manager keeps track of memory mapping, which applications are using which memory, page file management, and so on.)
This 4GB space is evenly divided into two parts, with 2GB dedicated for kernel usage, and 2GB left for application usage. Each application gets its own 2GB, but all applications have to share the same 2GB kernel space.
People who are unfamiliar with the real meaning behind the 4GB Windows memory limit often point out that certain versions of Windows (such as Enterprise or Datacenter editions) can actually support more than 4GB of physical memory. However, adding more than 4GB of physical memory to a server still doesn't change the fact that it's a 32-bit processor accessing a 32-bit memory space. Even when more than 4GB of memory is present, each process still has the normal 2GB virtual address space, and the kernel address space is still 2GB, just as on a normal non-PAE system.
However, systems booted /PAE can support up to 64GB physical memory. A 32-bit process can "use" large amounts of memory via AWE (address windowing extension) functions. This means that they must map views of the physical memory they allocate into their 2GB virtual address space. Essentially, they can only use 2GB of memory at a time.
By definition, a 32-bit processor uses 32 bits to refer to the location of each byte of memory. 2^32 = 4.2 billion, which means a memory address that's 32 bits long can only refer to 4.2 billion unique locations (i.e. 4 GB).
In the 32-bit Windows world, each application has its own “virtual” 4GB memory space. (This means that each application functions as if it has a flat 4GB of memory, and the system's memory manager keeps track of memory mapping, which applications are using which memory, page file management, and so on.)
This 4GB space is evenly divided into two parts, with 2GB dedicated for kernel usage, and 2GB left for application usage. Each application gets its own 2GB, but all applications have to share the same 2GB kernel space.
However, systems booted /PAE can support up to 64GB physical memory.
A 32-bit process can "use" large amounts of memory via AWE (address windowing extension) functions. This means that they must map views of the physical memory they allocate into their 2GB virtual address space. Essentially, they can only use 2GB of memory at a time.
Section 2.1.3
The Intel386™ Processor (1985)
The Intel386 processor was the first 32-bit processor in the IA-32 architecture family.
It introduced 32-bit registers for use both to hold operands and for addressing. The
lower half of each 32-bit Intel386 register retains the properties of the 16-bit registers
of earlier generations, permitting backward compatibility. The processor also
provides a virtual-8086 mode that allows for even greater efficiency when executing
programs created for 8086/8088 processors.
In addition, the Intel386 processor has support for:
• A 32-bit address bus that supports up to 4-GBytes of physical memory
• A segmented-memory model and a flat memory model
• Paging, with a fixed 4-KByte page size providing a method for virtual memory
management
• Support for parallel stages
3.1.1 Intel® 64 Architecture
Intel 64 architecture adds IA-32e mode. IA-32e mode has two sub-modes.
These are:
• Compatibility mode (sub-mode of IA-32e mode) — Compatibility mode
permits most legacy 16-bit and 32-bit applications to run without re-compilation
under a 64-bit operating system. For brevity, the compatibility sub-mode is
referred to as compatibility mode in IA-32 architecture. The execution
environment of compatibility mode is the same as described in Section 3.2.
Compatibility mode also supports all of the privilege levels that are supported in
64-bit and protected modes. Legacy applications that run in Virtual 8086 mode or
use hardware task management will not work in this mode.
Compatibility mode is enabled by the operating system (OS) on a code segment
basis. This means that a single 64-bit OS can support 64-bit applications running
in 64-bit mode and support legacy 32-bit applications (not recompiled for
64-bits) running in compatibility mode.
Compatibility mode is similar to 32-bit protected mode. Applications access only
the first 4 GByte of linear-address space. Compatibility mode uses 16-bit and 32-
bit address and operand sizes. Like protected mode, this mode allows applications
to access physical memory greater than 4 GByte using PAE (Physical
Address Extensions).
• 64-bit mode (sub-mode of IA-32e mode) — This mode enables a 64-bit
operating system to run applications written to access 64-bit linear address
space. For brevity, the 64-bit sub-mode is referred to as 64-bit mode in IA-32
architecture.
64-bit mode extends the number of general purpose registers and SIMD
extension registers from 8 to 16. General purpose registers are widened to 64
bits. The mode also introduces a new opcode prefix (REX) to access the register
extensions. See Section 3.2.1 for a detailed description.
64-bit mode is enabled by the operating system on a code-segment basis. Its
default address size is 64 bits and its default operand size is 32 bits. The default
operand size can be overridden on an instruction-by-instruction basis using a REX
opcode prefix in conjunction with an operand size override prefix.
REX prefixes allow a 64-bit operand to be specified when operating in 64-bit
mode. By using this mechanism, many existing instructions have been promoted
to allow the use of 64-bit registers and 64-bit addresses.
3.3.2 Paging and Virtual Memory
With the flat or the segmented memory model, linear address space is mapped into
the processor’s physical address space either directly or through paging. When using
direct mapping (paging disabled), each linear address has a one-to-one correspondence
with a physical address. Linear addresses are sent out on the processor’s
address lines without translation.
When using the IA-32 architecture’s paging mechanism (paging enabled), linear
address space is divided into pages which are mapped to virtual memory. The pages
of virtual memory are then mapped as needed into physical memory. When an operating
system or executive uses paging, the paging mechanism is transparent to an
application program. All that the application sees is linear address space.
In addition, IA-32 architecture’s paging mechanism includes extensions that
support:
• Page Address Extensions (PAE) to address physical address space greater than
4 GBytes.
• Page Size Extensions (PSE) to map linear address to physical address in
4-MBytes pages.
3.3.6 Extended Physical Addressing in Protected Mode
Beginning with P6 family processors, the IA-32 architecture supports addressing of
up to 64 GBytes (236 bytes) of physical memory. A program or task could not
address locations in this address space directly. Instead, it addresses individual linear
address spaces of up to 4 GBytes that mapped to 64-GByte physical address space
through a virtual memory management mechanism. Using this mechanism, an operating
system can enable a program to switch 4-GByte linear address spaces within
64-GByte physical address space.
The use of extended physical addressing requires the processor to operate in
protected mode and the operating system to provide a virtual memory management
system. See “36-Bit Physical Addressing Using the PAE Paging Mechanism” in
Chapter 3, “Protected-Mode Memory Management,” of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A.