Intel QPI speed relevancy

[secondplace]

I have a question regarding intels quickpath interconnect (qpi) technology.

how is the qpi affecting cpu speeds!?

i ask cause if i compare these two xeons:
E5506 running on 2,13GHz with 4,8gt/s (4mb cache, 80watt)
E5520 running on 2,26GHz with 5,86gt/s (8mb cache, 80watt)
that almost run at the same speed with only a diffrence of 0,13ghz but a major diffrence of 1,06gt/s.

will there be a significant speed improofment due to the raise of 1,06gt/s, or will the speed improofment only be due to the 0,13ghz raise?


also the price stages seem to be qpi based with a raise of 200$ +/- where in within same qpi range prices only diffrence around 50$ +/-

 

[sub mesa]

QPI replaces the old FSB architecture and changes the way the CPU communicates with the RAM memory. QPI is inspired by AMD's imc called HyperThreading, and replaces the old FSB architecture with a direct connection to the RAM.

Faster versions may offer more memory bandwidth, but it depends on your applications whether this will benefit overall performance in a meaningful degree. The biggest change comes from having QPI instead of having FSB, just some more GT/s will make workloads like rendering faster, and other memory-hungry workloads.

 

[spud]

QPI replaces the old FSB architecture and changes the way the CPU communicates with the RAM memory. QPI is inspired by AMD's imc called HyperThreading, and replaces the old FSB architecture with a direct connection to the RAM.

Faster versions may offer more memory bandwidth, but it depends on your applications whether this will benefit overall performance in a meaningful degree. The biggest change comes from having QPI instead of having FSB, just some more GT/s will make workloads like rendering faster, and other memory-hungry workloads.

QPI was inspired by DEC's Alpha which makes sense since Intel bought the division from HP, second of all Hyper Threading is a Intel technology also came with the deal with DEC. AMD's solution is called Hyper Transport.

 

[sub mesa]

Ah yes meant HyperTransport, confusingly both can be called HTT. Though QPI and HyperTransport are technically not alike, the motivation for Intel to do it and the need to hurry with it was clearly prompted by AMD, same with integrating AMD64 spec; if it had been Intel's choice it would have taken much longer before consumers were having 64-bit systems.

 

[Wisecracker]

Xeon E5506: DDR3-800

Xeon E5520: DDR3-1066

 

[archibael]

QPI replaces the old FSB architecture and changes the way the CPU communicates with the RAM memory. QPI is inspired by AMD's imc called HyperThreading, and replaces the old FSB architecture with a direct connection to the RAM.

QPI is the interconnect between CPU and the northbridge (which at this point is just a glorified PCIe hub and passthrough to the southbridge when you're in uniprocessor mode) . It has essentially nothing to do with RAM in the conventional sense*. The on-die memory controller on the CPU != QPI.




* You could be pendantic and say that QPI carries information from the memory to the PCIe and other I/Os, but typically memory throughput between the CPU and the DIMMS is the relevant metric.

 

[secondplace]

let me try to round this up

basically for intensive tasks (cad/3d/rendering) a cpu with higher qpi rate will be somewhat faster.

but for tasks with less workload there is no noticeable speedimproofment.


did i get this right?

 

[Wisecracker]

let me try to round this up

basically for intensive tasks (cad/3d/rendering) a cpu with higher qpi rate will be somewhat faster.

but for tasks with less workload there is no noticeable speedimproofment.


did i get this right?

Sorta.

You need to think of QP more in terms of a "link data rate" than speed (it's a silly distinction but bear with me).

The old Intel FSB theoretical max was 1.6 GT/s - a 'quad-pumped' single bi-directional 400MHz bus. The old FSB was starting to become a bottleneck. ""GT/s"" simply measures the theoretical bandwidth across the CPU interconnects to the rest of your system.

QP interconnects consist of multiple parallel links which are faster but the increase in speed you are seeing is from higher bit rates/transfers across a 'wider bus'.

When you think of QP it is better to think of theoretical bandwidth --- with all things being equal in your rig a 'larger' theoretical QP rate will not necessarily be faster if you are not 'starving for bandwidth' in the first place.

They way we looked at it with AMD, as long as your HT rate exceeded your memory 'rate' you were good to go (pretty simplistic but I think you get the point). I assume it is pretty much the same with QP with a few other minor distinctions.

And I will also assume that Intel (like AMD) will see a greater gain in performance (increased bandwidth and reduced latency) from increasing the speed of the integrated memory controller --- I haven't tested it and don't really know but that would be a decent 'edumacated' guess ...

 

[secondplace]

thanks for your explanation

 

[sharanbr]

Archibael,

In some places QPI is described as a processor to processor interface (in multi socket systems). That made me wonder why a processor to processor communcation would need such high bandwidth in the first place. This & your response throws some more questions.

1) It appears that QPI can be used both for south bridge and for processor-processor communication.
If QPI is used for south bridge (or PCH) then what would be used for processor-processor communcation (DMI?)

2) If QPI is targeted for processor-procesor communcation then would such a high bandwidth link be needed for processor-processor communication?

If experts like Archibael can weigh-in, I would be thankful ...

 

[VincentP]

As archibael noted, QPI is not used to interface between the CPU and memory.
CPUs that include a QPI link always have an integrated memory controller.

QPI is used to link processors to the motherboard chipset.
QPI can also be used to connect to other processors.
A QPI link is one to one, so a processor needs one link for a single processor system, 2 links for a dual processor system and 4 links for a quad processor system.
Intel sells different series of Xeon processors for dual and quad processor systems that have the required number of QPI links.

For a single processor system, the QPI link is used to carry all bandwidth between the processor and the PCI-E lanes of the motherboard chipset as well as any bandwidth for the usb, sata and any other I/O which is connected to the south bridge. Link from processor to chipset is QPI, link from chipset to south bridge is DMI.

This is different to most Intel desktop processors where 16 PCI-E lanes are integrated into the CPU and only a DMI interface is included to communicate with the PCH. The PCH then has some PCI-E lanes and other I/O. These processors do not have a QPI link.

In general, you won't need to worry about the bandwidth provided by the QPI link. It will be more than enough to service the provided PCI-E lanes of the chipset and I/O of the south bridge.

The particular processors you have listed are old Nehalem EP processors, the same generation as the original core i7, i5 and i3 processors.
These both have two QPI links, so are suitable for one or two processor systems.
The E5520 has the following advantages:
- Faster base clock speed (2.26 GHz rather than 2.13 GHz)
- Turbo-boost (up to 2.53 GHz, not supported on the E5506)
- Larger cache (8 MB rather than 4 MB)
- Hyper-threading (not supported on the E5506)
- Faster memory support (DDR3-1066 rather than DDR3-800)
- Faster QPI link (5.86 GT/s rather than 4.8 GT/s)

The E5520 is a much better processor, but the extra QPI link speed is the least important reason.

 

[sharanbr]

Thanks, Vincent. I have one question though specifically on Xeon processors.

Is it not that most of the north bridge function is not integrated within the processor itself and only south bridge is outside.
I am asking this question since you mentioned about chipset and south bridge in your response

 

[VincentP]

Thanks, Vincent. I have one question though specifically on Xeon processors.

Is it not that most of the north bridge function is not integrated within the processor itself and only south bridge is outside.
I am asking this question since you mentioned about chipset and south bridge in your response

North bridge and south bridge chipsets is an architecture that intel used for many years, but not any more.
This old architecture had an FSB from the CPU to the north bridge. The north bridge included the memory controller and ISA/PCI/AGP/PCI-E. The north bridge handled remaining I/O.

They currently have two different architectures:
LGA 1156/1155/1150 platforms with have memory controller and 16 lanes PCI-E on the CPU and remaining I/O from the PCH. This PCH is similar to the old south bridge but also has an additional 4 lanes PCI-E and PCI bus.

LGA 1366/2011 platforms (including all Xeon processors) which have a memory controller on the CPU, but no PCI-E lanes. The motherboard chipset, sometimes still called the north bridge but not by Intel, contains the main PCI-E lanes (usually 40 lanes rather than only 16 on the LGA 1156/1155/1150 platforms) and some other functionality. It uses a south bridge chipset for remaining I/O.

Both these architectures move the memory controller from the old north bridge to the CPU.
Additionally, the LGA 1156/1155/1150 architecture moves the main PCI-E lanes to the CPU as well (usually used for graphics). This is cheaper for mainstream systems.

The LGA 1136/2011 retains some of the old north bridge functionality in the motherboard chipset. This architecture requires a much higher bandwidth from the CPU to the chipset than the other architecture because of the PCI-E lanes, so they use QPI. These additional PCI-E lanes are the major benefit of this architecture. These can be used for multiple graphics cards or more commonly in servers for RAID controllers.

 

[sharanbr]

A QPI link is one to one, so a processor needs one link for a single processor system, 2 links for a dual processor system and 4 links for a quad processor system.

I am assuming that by dual processor system, you mean systems with 2 CPU sockets. In that case, one would need just one QPI for one processor to talk to another. Why would there be a need for 2 QPI links?

 

[VincentP]

A QPI link is one to one, so a processor needs one link for a single processor system, 2 links for a dual processor system and 4 links for a quad processor system.

I am assuming that by dual processor system, you mean systems with 2 CPU sockets. In that case, one would need just one QPI for one processor to talk to another. Why would there be a need for 2 QPI links?

Yes, a dual processor system has two CPU sockets.
Each processor requires two QPI links. One of these on each processor is used to communicate with the motherboard chipset, the second link is used to communicate with the other processor.