AMD sketches out two new x86 cores: Meyers' Vision

A separate design called Ontario will use two Bobcat cores, a DX11 GPU and DDR3 memory. However, AMD is not revealing in what process it is making the chip which is aimed at thin and light notebooks and netbooks.

Software, fab and finance challenges: Synthesizable Atom killer and two-in-one core due in 2011

Both chips will ship in volume in 2011 along with Zambezi, high-end desktop chips using four to eight of the Bulldozer cores, but no integrated graphics. Bulldozer will also show up in two server processors in 2011.

"Intel is ahead in process technology and doesn't face AMD's financial challenges as the two compete with roughly similar architectures. AMD executives referred to a still-evolving programming model for its integrated chips as a strategic differentiator.
"Fusion is not just CPU and graphics on the same die," said Dirk Meyer, chief executive of AMD, speaking at an annual analysts meeting here. "The vision is to enable new data-parallel applications to run on the most power-efficient core possible, and that's where our vision differs from Intel's," he said."

http://www.eetimes.com/showArticle [...] 364&pgno=3

UltraSPARC T1 and T2 performance:
"The primary goal of Zambezi was to have the minimum latency for data crossing the ASIC. The final Zambezi latency achieved was a mere 33.1ns which exceeded our expectations. Approximately a third of the 33ns is serialization/deserialization overhead, and another third is link-layer overhead (framing composition/decomposition, CRC check/generate, etc.)

Note the Zambezi is involved even for local access to memory in order to resolve conflicts. The local memory latency, therefore, for the T5440 which is 229ns is slightly higher than the T5140 and T5240. The remote memory latency for the T5440 is 311ns. This makes the T5440 a NUMA machine but not highly so.

The bandwidth achieved by the Zambezi is extremely impressive. The theoretical bandwidth from our simulations is 84GB/s read, 42GB/s write and 126GB/s combined.

Translating these speeds and feeds to the real world the T5440 has achieved many world record benchmark results. These results all demonstrate the highest levels of throughput and scalability. Zambezi is THE key component in this scalability." http://blogs.sun.com/deniss/entry/zambezi_architecture same as above

While we are here pounding the AMD Zambezi Drum...

There is a discussion on at SA. The two discussions are ongoing at the same time. The following is the SA discussion.
If it is offensive say so and I will delete it. The comparisons are interesting...

http://ecsdl.org/dbt/dbt.jsp?KEY=J [...] ISS#MAJOR8

no it isnt a full node is a 50% shrink 16 nm isnt 50% from 22nm

Edit : I am in err here

http://www.itrs.net/Links/2005Wint [...] -Final.pdf

I always admit err

lol you have known me a few years john, when I am wrong I face it.

I said it 4 years ago I'll say it again its good to be wrong once in a while as long as you dont defend it with ignorance . The bad taste of boot leather and crow fades away after a few days.

ITRS "full" node shrinks are roughly the current node divided by the square root of two. The idea behind that is to have a full node shrink reduce the die space required to fab the same number of transistors by half.

I was doing OK until Meyer got to data-parallel applications: It looks like I've gotta get some help...
"MIMD computers are notoriously difficult to program. Data-Parallel Programming demonstrates that architecture-independent parallel programming is possible by describing in detail how programs written in a high-level SIMD programming language may be compiled and efficiently executed-on both shared-memory multiprocessors and distributed-memory multicomputers."

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