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QPI and DMI - I Don't Get the Math

Mind you, I was never that good at math in school. Here's my problem:

The QPI bus (in the X58 Express chipset) provides a whopping 25.6 GB/s of bandwidth to the I/O Hub for PCIe video and - presumably - to connect the CPU with the ICH10 Southbridge...but the Southbridge connects to the I/O Hub with a relatively narrow 2 GB/s DMI bus.

What's the point of 25.6 GB/s if no more than 2 GB/s gets to the Southbridge?

Seems like I'm fundamentally misunderstanding something. I'll be grateful if someone could straighten me out.
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  1. Best answer
    For many years chipsets have been organized as a high-speed "North Bridge" and a slower speed "South Bridge". The North Bridge is used to interconnect the CPU with high-speed devices such as RAM and the video graphics port (originally AGP, now PCIe). The South Bridge is used to interconnect the CPU with slower-speed devices such as USB, Network, etc.

    The only real difference with X58 is that the RAM controller has been moved into the CPU itself for even faster access. The high-speed connection to the North Bridge is still required for the wide PCIe slots, and the stuff on the South Bridge doesn't generally need that kind of throughput.

    Also, don't forget that QPI is a general-purpose interconnect that is also designed to handle multiple CPU chips connected to multiple DRAM banks - that high bandwidth is important for multi-way communications in a multi-processor system.
  2. An informative and succinct explanation...thank you!
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