IGNORE THIS POST (testing, 1, 2, 3...)

...testing completed...

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  1. $%#@ clicked the wrong button, again [:bilbat:6]
  2. Over 100 reads. I don't think any of us are doing a good job ignoring your work in progress. I know I'm looking forward to the finished product.
  3. I know you said to ignore, but I just wanted to say it looks like a great start. I just updated my BIOS today and ran into one interesting problem. I loaded optimized and rebooted, however when I got in it reported my CPU temp was 6C. It wasn't until I adjusted more settings and rebooted again it reported properly. Just a random tidbit of info.
  4. Quote:
    Over 100 reads. I don't think any of us are doing a good job ignoring your work in progress.

    I know you said to ignore...

    Just goes to show how bad everyone in this %^#$ forum is at following instructions [:bilbat:9] [:bilbat:9]

    All kidding aside, I'd be glad for help, suggestions, topics that should be covered, critiques... Lets see; five Tom's Points for every misspelling caught; ten for excessive or misused puctuation; twenty-five for every error of fact! Like, I could give out points, and anyone else would ever care about them [:bilbat:5]
  5. You've given good information on the merits of AHCI or not before and that's probably worth including.
  6. Good point - I'll include a little 'which ports are which, and what to use 'em for', as well... That seems to be the source of endless confusion!
  7. Looking good so far. You've already got two of the more common questions of late covered - how to update BIOS (and more importantly how not to update bios), and the missing memory mystery. Is it worth mentioning somewhere what slots the memory on the recent Intel boards goes in? I.e., Gigabyte's slot 1 is actually the second physical slot from the CPU and slot 3 is the fourth slot? I know the trick if you start going down the memory path is it'd be very easy to get off track, but you already had a note about updating BIOS for the new chipsets so not totally off track.
  8. Hmm, here's a mystery/potential typo for ya. What is the correct way to refer to the company?

    I see, you used: "GigaByte"
    Some sites use: "Gigabyte"
    And a brief perusal of their website (and a glance at my 3 GB boxes) show: "GIGABYTE" (always in all caps).
  9. Shameless 'bump' - think I've gotten a couple of your suggestions - still working on USB grief and BootLoops - halfway through SATA/AHCI/RAID stuff - will post soon...
  10. It's coming together nicely. I had a couple thoughts as I was reading through it again, and of course I forgot one of them already. Oh well. The one I remember is - are you going to throw in your standard advice to set the floppy as the first boot device in case of disaster?
  11. Quote:
    are you going to throw in your standard advice to set the floppy as the first boot device in case of disaster?

    Ya know - I've been debating that with myself (one of the good things about being fairly crazy :pt1cable: , you've always got someone handy to debate with!) I know the 'fan-boiz/gamer-kidz' think floppies are something us antiquated geezers [:bilbat:6] carried in our shirt pockets when we rode our dinosaurs to work in the 'olden days'; and a lot of cases these days don't even have a place to put one; but - when you need one, you really need one!

    Everything 'tech': pre-load driver installs, saving CMOS to an external (or, more importantly, loading it back!), the rescue 'blind-flash', and umpteen bootable utilities - 'wants' a floppy, works with a floppy 'no-effort', and just makes life all-around easier!

    The other 'against' issue, is that with the 1156/1366, the BIOS went to 2meg, so the 'blind flash' is history for those...

    I'm thinking, with your vote, the tie is broken, two to one, in favor! (...but don't be expecting any medicaid 'set-asides' for your vote!!) [:bilbat:9]

    I had a couple thoughts as I was reading through it again, and of course I forgot one of them already

    ...broken interrupt return mechanism... [:bilbat:2] Happens to me three times a day - this process reminds me of doing 'brain-dumps' after the MCSE exams! You just reminded me of another thing - gotta have a thingie extolling the virtues of adding that lousy two-dollar case speaker!!
  12. Well bilbat, I don't know if you saw, but in another thread your 'bent pin - missing ram' fix worked again. Just out of curiosity, have you ever seen that show up on a 1156 board?
  13. Oh yeah it's shown up in a number of cases on an 1156. I was keeping a list of 3 or 4 handy for a while to refer people to, but seem to have misplaced it. I've noticed probably at least one a week.
  14. Wow, so is it one channel missing in those cases too or instability?
  15. The Intel guide to installation/examination that I alway cite is actually 'aimed at' 1156s:
    though applicable to both sockets...
  16. What, you used invisible ink? :lol: :lol:
  17. Ackk - 'nother bad click... But what isn't a bad click is really ticking me off. Tom's here has been stumbling and stuttering for days now, recently was down for hours, and now, an edit has somehow relaced every 'img' tag with a 'url' tag, and obliterated every image! [:bilbat:3]

    ...god. I hate Java programmers [:bilbat:7]
  18. Oh, now I understand why the guy said "even though he had a 1366 it was helpful" Even after I had glanced over the link it didn't quite click that it was for 1156 (even though I have an 1156).
  19. One more 'bump' - getting there! Any more topics, anyone?
  20. Looking good. I can't wait to see the USB woes section, every time it's not included the suspense builds. A few thoughts:

    1. A comment about this sentence: "You may not be seeing some of this if you have the boot 'splash' screen enabled (see BIOS - General Settings above) this will allow you to 'see' more of what's going on..." -- it's not clear what will allow them to see more.

    You may want to clarify by adding one word: "You may not be seeing some of this if you have the boot 'splash' screen enabled (see BIOS - General Settings above); disabling this will allow you to 'see' more of what's going on..."

    2. Under "Sorting out SATA" you get into "and then you need to put in the AHCI 'pre-load' drivers - this is easiest done during the OS install - it's a nasty, more complicated job to add 'em to an already installed system... "
    Is it worth mentioning that this procedure is unnecessary with Windows 7? Many new builders, especially as more time passes and as they move to the latest OS, will find that this whole overcomplicated process is no longer necessary.

    3. This may be more of a question than a comment but I got to thinking while reading your "Sorting out SATA" section - I actually disabled the secondary chip, the "Onboard SATA/IDE Device". I only have two harddisks plus a DVD drive and I've plugged them into the main SATA ports. If you don't have enough drives to even fill up all the southbridge SATA ports, is it a good idea to connect everything to the southbridge and turn off the secondary chip?

    4. This is just an editing comment, at the bottom of your Sorting out SATA section there's some edit tags showing, you can see two tags (and both are opening tags) in a section thats already in italics:
    always want this setting at "Enabled" - it turns on
  21. I will catch most of these...

    Probably worth mentioning that the AHCI drivers are 'native' to seven - what I don't know for sure is whether they're all 'native' (GSATAs and Marvells), or if its just the southbridge ports... Hesitant to mention it until I find out for sure :pt1cable:

    I actually disabled the secondary chip, the "Onboard SATA/IDE Device". I only have two harddisks plus a DVD drive and I've plugged them into the main SATA ports. If you don't have enough drives to even fill up all the southbridge SATA ports, is it a good idea to connect everything to the southbridge and turn off the secondary chip?

    Always best to disable anything you're not actually using - saves interrupts, discovery, and interrupt services...

    'Nother interesting (but esoteric) optimization for the ICH's - if you're only using a couple ports, and neither using RAID or AHCI, they're best 'split' with one drive on port 0-3, and the second on 4 0r 5 - from "Intel® I/O Controller Hub 10 (ICH10) Family Datasheet" (Page 176):
    5.16 SATA Host Controller (D31:F2, F5)
    The SATA function in the ICH10 has three modes of operation to support different operating system conditions. In the case of Native IDE enabled operating systems, the
    ICH10 utilizes two controllers to enable all six ports of the bus. The first controller (Device 31: Function 2) supports ports 0–3 and the second controller (Device 31: Function 5) supports ports 4 and 5. When using a legacy operating system, only one controller (Device 31: Function 2) is available that supports ports 0 - 3. In AHCI or
    RAID mode, only one controller (Device 31: Function 2) is used enabling all six ports.

    Now, whether you'd gain by putting the HDs on, say, 0 and 4, and enabling the jMicron to handle the DVD - only testing would tell; what you gain in raw port speed, you might lose in interrupt service...

    As for 4, I'm laughing [:bilbat:9] When I did the 'refresh' after the last edit, I noticed that at the same time I saw your post regarding it - was just 'headed back in' to fix it!
  22. OK - I think were getting pretty close to "ready for prime time" here!!


    Any last minute topics missed? Errors in: fact? spelling? grammar & punctuation (beside, of course, my usual, rambling, ellipsis-ridden 'style' - or lack, perhaps, thereof [:bilbat:2] )

    Got another trouble that I'd like to see if someone can confirm for me - and, maybe, point out my troubles :cry:

    I keep getting 'smiley' tags that don't show pictures of the sticky! I'm losing my mind in general, as:

    -at first, it seemed like it was a particular 'spot' where they wouldn't work - I tried moving 'em around endlessly, and searched for a somehow 'disrupted' tage before or after, forever! 'till my eyes are bleeding...

    -then I thought there may be a 'limit' on how many you can use, but that didn't seem to be it - some seem to work, some not...

    -then I thought maybe it was 'user' tags that were limited - the :usename:# tags - that didn't pan out either...

    -sometimes it seems like the last couple edited have the problem, but never consistently...


    I've tried:

    -flushing my browser cache...

    -using a different browser...

    -updating my Sun Java...

    I'm ready for the nets!!! [:bilbat]

    Main thing - can someone else confirm for me that they're seeing the same thing I am??
  23. Yes, I am seeing several not work as well. I thought there was a limit (though as I have never written such a long post, I don't really know). PM someone like Randomizer, he should know I'd think.
  24. I know this may be trivial but it's bitten me before and I forgot about it until recently when I updated the BIOS on my GA-EP45-UD3R.

    Put the updated BIOS on a floppy and updated. The QFlash utility reported a checksum (I don't see any place to check that but maybe I am not looking in the right place) as well as a successful verification and flash.

    Rebooted only to find the dreaded BIOS checksum error. Hmmm. Tried again.

    Believe it or not, I got a different checksum but the same error. Oh oh.

    So I took another floppy and repeated the procedure. Lo and behold! It worked.

    The difference? A bad floppy the first time and, upon review, I could hear the difference between the two as the BIOS was being written and read. Clearly the first floppy was bad.

    Moral of the story: Use a good floppy disk.
  25. I've 'dumped' a BIOS twice in a row - the same exact way, with a different cause... It's one reason I'm so confident in the 'dual BIOS' recovery mechanism - so long as you haven't 'futzed around' with @BIOS! I flashed a 'bad' BIOS, and just assumed it was just a bad floppy - so, made another, and shot myself in the other foot! I could not believe it would even attempt to load a 'bad one', due to checksumming. Turned out I had a corrupted download - d/l'd it from another source - worked fine... Suggesting I cover this in the 'sticky'? I think it's pretty close - seem to have gotten rid of my format troubles; it is limited to ten sets of 'img' tags, and the 'smileys' seem to have some 'overall' byte limit - past that, the tags start randomly malfunctioning,,, &^%$ Java programmers anyway!
  26. bilbat said:
    Main thing - can someone else confirm for me that they're seeing the same thing I am??

    I see all formatting correctly, all bold is bold, all underlines are there and I can see all the emoticons. No images appear to be missing. Unless I actually can't see it in which case I don't know it's missing.

    So it looks right to me. I am using Firefox 3.0.18 with AdblockPlus and NoScript and it all looks right to me.
  27. bilbat said:
    I've 'dumped' a BIOS twice in a row - Suggesting I cover this in the 'sticky'?

    Not really sure what I am suggesting. I know you've essentially covered the Gigabyte specific ills with @BIOS but you might just want to add a small subset of items to look for like:

    If a BIOS flash seems to fail with errors even though the flash appeared to work right, check the following:

    - Download it again and make sure the download was correct (how they do this is unknown without a checksum from Gigabyte)
    - Check that the floppy is good
    - Ensure your floppy drive is in good working order (confirm the cable is connected correctly and the power cable is firmly attached)
    - Try again and check the checksum value reported. Confirm it's the same as the first time you tried and, if different, download it again and try a different floppy.

    Something along those lines. Quick and dirty to give a nudge towards checking their process and try again.

    Like I said, not critical. Just something that happens and it's good to have a quick blurb rather than nothing.

    Up to you.
  28. [:isamuelson:6] I think you did the actual work for me [:bilbat:9] Take a look...
  29. Looks good to me!
  30. On a quick glance I no longer see any not working icons either. They certainly were some before though.
  31. I miss 'em, too :cry: But, what works - works! I think it's ready for the magic 'sticky' wand to be waved over it...
  32. I think so. You'll get more feedback then too. I also think it looks very clear, despite having a lot of text (something randomizer rightfully wanted). I know I've used it/referred others here several times already.
  33. When the sticky gets gratned you should put a link to it in your original post in case google sends anyone in here.

    All this talk about CHECKSUMs has me wondering, actually always wondered but never bothered to ask before, sometimes when I'm updating my BIOS it tells me what the CHECKSUM is and asks if I want to continute. This makes me wonder two things:
    1. Why doesn't it show me the checksum every time I upgrade BIOS?
    2. How do I know if this is the right checksum? I've never seen it provided by Gigabyte so I always figured I'm taking a blind leap of faith and just hit continue. Is there some place I should be shown the checksum, maybe when I download the BIOS files?

    EDIT: Just found the to-be sticky post. Looks great. Not to be overly picky here but since you put so much work into it, as I was casually glancing through I noticed a very, very minor typo. In the first paragraph under USB woes, need a space between the words the & BIOS in the sentence that starts out: "On theBIOS'"
  34. Thanks - you've got sharp eyes! Fixed it, and will post a link to original immediately...

    As for checksums - ?????

    I will try to find out... I've been trying to 'get through' my project list - at least a little bit! Manic-depressives are well known for starting ten million 'projects' - - - and never finishing any [:bilbat:9] Now that the sticky (which I've been 'meaning to do' for six months) is up, I'm hoping the simple repetitive questions here will be reduced, and I can devote some time to other things. Among them - I want to try to get hold of someone at GB marketing, and point out to them that it would be useful (and profitable) to them if I could occasionally be given access to some high-level support people/engineers in Taiwan, as this sort of thing
    If fan control still can not work after VGA bios update, can you send back the card to the shop or dealer for second opinion or RMA.

    is winning them no friends!
  35. clickme

    [label=anywhere] i be here...[/label]
  36. Invisible ink again, bibat?.... :lol:
  37. Just trying to figure out some tagging tricks...
  38. huh....? :o What do you mean by tagging?
  39. [cpp]bold

    I'm looking for a 'jump' tag, like HTML's <a href>, that will allow me to have a click in one place in a given post, take the reader to a different place in the same post...

    [anchor=Topic01]"Some text..."[/anchor]
    blah blah...
    blah blah...
    blah blah...
    blah blah...
    [jump=Topic01]"Jump label text"[/jump]

  40. To make a bootable USB flash-drive:

    First, download the HP USB Disk Storage Format Tool - v2.1.8 (or here, or here, in case of an eventual 'boken link')...

    Then, you will need the system files; download here, and unzip the file to a directory/folder whose name you will remember; or, download this, which is an executable, that will 'unzip' its contents automatically when you double-click on it...

    Running the installer for the HP utility will result in this icon:

    (names have been change to protect the innocent - or, in this case, the obsessive; I have, at last count, two-hundred-fourty-three shortcuts, spread across four monitors, and I just can't stand shortcuts with a name longer than two lines [:jaydeejohn:3] )

    Double-clicking the shortcut will result in this:

    You can't accidentally format your hard drive with this thing, but I don't want to hear any whining about having erased poor, dead, Aunt Bessie's pictures from your camera's SD stick, or having formatted your iPod by mistake, so check that the first item 'points' to your actual flash drive - do it now!

    Make sure the 'FAT 32' file system is selected; any volume name (or none) will do; check the 'Create a DOS startup Disk' box; and click on the '...' button to navigate to the set of 'system files' you unzipped earlier... Then, 'Start' to let 'er rip!! It will take a bit - on a 3.8GHz 9550 with an eight gig (very fast) HyperX, the full format takes roughly twelve minutes. I haven't verified whether the 'quick format' option works properly - I don't think flash is predictable enough to chance it, especially if you're planning on using it to 'auto-load' a BIOS burner! When it's done, it will present you with a summary:

    and opening the drive location should show you something akin to this:
  41. ...just another 'formatting' check... ignore for now

    Memory - Part I

    Since the advent, and common use of DDR3 memory, with its huge variety of available frequencies and latencies, memory selection and use has become an on-going nightmare for many. One thing repetitive questions have made apparent is that the more you've paid for your RAM - the le$$ likely you are to be able to get it to work acceptably! This is unfortunate - and unnecessary! I have thought, for some time (pretty much since the first i7 problems started cropping up), to try to put together a comprehensive guide to making an informed decision about buying RAM - and then, being able to actually get it working!!

    I know people these days, on average, are to some degree 'math-phobic', so I will keep the formulae and calculations to a minimum - but - I will work out some 'examples', and will provide an evaluation tool to 'get the math done', as it's the only way to actually know anything about prospective purchases!

    A great deal of the information contained, as well as most of the great illustrations, have been 'extracted' from "What Every Programmer Should Know About Memory" by Ulrich Drepper of RedHat, Inc.; the original PDF can be found here. I cannot recommend this document highly enough; however, it is 'aimed at' the more 'mechanical' details of memory (and especially CPU cache) access, and how to optimize these to get responsive, efficient programs; thus, contains a large amount of detail (114 pages!) that many will find mostly irrelevant...

    One last comment before the start - the text contains a number of occurrences of the term “usually” and other, similar qualifiers. The technology discussed here exists in many, many variations in the real world and this discussion only addresses the most common, mainstream versions. It is rare that absolute statements can be made about any 'current' (which means 'evolving'!) technology, thus the qualifiers...

    What memory is, and how it works:

    The following discusses hardware details at the gate level and the access protocol between the memory controller and the DRAM chips. Users will likely find this information enlightening since these details explain why RAM access works the way it does, and relates directly to the purchasers' price/perfomance decisions.

    The first interesting details are centered around the question: why there are different types of RAM in the same machine? More specifically, why are there both static RAM (SRAM²) and dynamic RAM (DRAM)? The former is much faster and provides the same functionality. Why is not all RAM in a machine SRAM? The answer is, as one might expect, co$t. SRAM is much more expensive to produce and to use than DRAM. Both these cost factors are important, the second one increasing in importance more and more. To understand these differences we look at the implementation of a 'bit' of storage for both SRAM and DRAM:

    Static RAM:

    shows the structure of a 6 transistor SRAM cell. The core of this cell is formed by the four transistors M1 to M4 which form two crosscoupled inverters. They have two stable states, representing 0 and 1 respectively. The state is stable as long as power on Vdd is available.

    ² other contexts SRAM might mean “synchronous RAM”.

    For the following discussion it is important to note that:
    a 'cell' (bit) needs six transistors - variants with four exist, but they have disadvantages...
    maintaining the state of the cell requires constant power...
    the cell state is available for reading almost immediately once the word access line WL is raised...
    the signal is as rectangular (changing quickly between the two binary states) as other transistor-controlled signals...
    the cell state is stable, no 'refresh' cycles are needed...

    Dynamic RAM:

    Dynamic RAM is, in its structure, much simpler than static RAM. All it consists of is one transistor and one capacitor. (For you 'non-electronic' types - a capacitor is sort of like a tiny 'battery' - it 'holds a charge', which of course means that it can be 'charged' and 'discharged'... Just as an aside, they're not all 'tiny and inocuous'; I have water-glass-sized kilovolt electrolytics laying around whose 'discharge' can kill you!!) This huge difference in complexity of course means that it functions very differently than static RAM.

    A dynamic RAM cell keeps its state in the capacitor C. The transistor M is used to guard the access to the state. To read the state of the cell, the access line AL is raised; this either causes a current to flow on the dataline DL or not, depending on the charge in the capacitor. To write to the cell, the data line DL is appropriately set and then AL is raised for a time long enough to charge or drain the capacitor.

    There are a number of complications with the design of dynamic RAM. The use of a capacitor means that reading the cell discharges the capacitor. The procedure cannot be repeated indefinitely, the capacitor must be recharged at some point. Even worse, to accommodate the huge number of cells (chips with 10 to the 9th, or more, cells are now common) the 'capacity' of the capacitor must be low (in the femto-farad range or lower). A fully charged capacitor only holds a few tens of thousands of electrons. Even though the resistance of the capacitor is high (a couple of tera-ohms), it only takes a short time for the capacity to dissipate. This problem is called “leakage”.

    This leakage is why a DRAM cell must be constantly refreshed. For most DRAM chips these days this refresh must happen every 64μs, or oftener. During the refresh cycle no access to the memory is possible since a refresh is simply a memory read operation where the result is discarded. For some workloads this overhead might stall up to 50% of the memory accesses.

    A second problem resulting from the tiny charge is that the information read from the cell is not directly usable. The data line must be connected to a sense amplifier which can distinguish between a stored 0 or 1 over the whole range of charges which still have to count as 1.

    A third problem is that reading a cell causes the charge of the capacitor to be depleted. This means every read operation must be followed by an operation to recharge the capacitor. This is done automatically by feeding the output of the sense amplifier back into the capacitor. It does mean, though, the reading of memory content requires additional energy and, more importantly, time.

    A fourth problem is that charging and draining a capacitor is not instantaneous. The signals received by the sense amplifier are not 'rectangular', so a conservative estimate as to when the output of the cell is usable has to be used. The formulas for charging and discharging a capacitor are:

    This means it takes some time (determined by the capacity C and resistance R) for the capacitor to be charged and discharged. It also means that the current which can be detected by the sense amplifiers is not immediately available. Figure 2.6 shows the charge and discharge curves:
    The X–axis is measured in units of RC (resistance multiplied by capacitance) which is a unit of time. Unlike the static RAM /CASe where the output is immediately available when the word access line is raised, it will always take a bit of time until the capacitor discharges sufficiently. This delay severely limits how fast DRAM can be. If there is one concept I want you to 'take away' from this section, this it: underlying DRAM operation are physical processes that take finite, calculable amounts of time!!

    The simple approach has its advantages, too. The main advantage is size. The chip 'real estate' needed for one DRAM cell is many times smaller than that of an SRAM cell. The SRAM cells also need individual power for the transistors maintaining the state. The structure of the DRAM cell is also tidier and more regular, which means packing many of them close together on a die is simpler. Overall, the (quite dramatic) difference in cost wins. Except in specialized hardware – network routers, for example – we have to live with main memory which is based on DRAM.

    a 'cell' (bit) needs one transistor, but depends upon a capacitor, whose charge/discharge take time...
    maintaining the state of the cell requires periodic 'refreshing' of its state...
    the cell state is available for reading only through/after discharge/amplification...
    the signal/content is a 'curve' (changing less quickly between the two binary states) compared with 'rectangular' transistor-controlled signals...

    Next, we need to look into a few more details of the actual use of DRAM cells.

    DRAM organization and access:


    No explanation of 'what's going on with' your RAM can be made without a preliminary, cursory explanation of the use of 'multiplexing'. Multiplexing, simply described, is a means of using a limited number of transmission means (board signal traces, connector pins, cables' individual wires, connecting elements inside a chip...) to transmit a larger number of actual signals. In its simplest form, it can be shown as a 'gating' mechanism that is functionally equivalent to a two-pole switch:

    In more complex forms, any number of signals, on any number of transmission lines, can be multiplexed ('MUXed', to geeks - the corresponding 'decode' is to 'DEMUX'):

    A program selects a memory location using a 'virtual address' - the CPU 'translates' this into a physical address, and finally the memory controller selects the RAM chip and cells corresponding to that address. To select the individual memory cell on the RAM chip, parts of the physical address are passed on in the form of a number of electrical address lines.

    It's impractical to address memory locations individually from the memory controller: 4GB of RAM would require 2-to-the-32nd address lines (4,294,967,296!). Instead, the address is 'passed' encoded as a binary number using a smaller set of address lines. The address passed to the DRAM chip this way must be demultiplexed first. A demultiplexer with 'N' address lines must have '2N' output lines. These output lines can be used to select the memory cell. Using this direct approach is no big problem for chips with small capacities.

    But, if the number of cells grows, this approach is not suitable - 1Gbit capacity would require 30 address lines and 230 select lines. The size (and co$t) of a demultiplexer increases exponentially with the number of input lines when speed is not to be sacrificed. Even more importantly, transmitting 30 impulses on the address lines synchronously is much harder (and, again, more co$tly!) than transmitting “only” 15 impulses. Fewer lines have to be laid out at exactly the same length (or 'timed' exactly)...

    /RAS and /CAS

    - a DRAM chip at a very 'high level'... The cells are organized in rows and columns. They could all be aligned in one row, but then the chip would need a huge demultiplexer. With the 'array' approach the design can get by with one demultiplexer and one multiplexer of half the size. This is a huge saving on all fronts. In the example, the address lines a0 and a1 through the row address selection (/RAS) demultiplexer select the address lines of a whole row of cells. When reading, the content of all cells is thus made available to the column address selection (/CAS) multiplexer. Based on the address lines a2 and a3, the content of one column is then made available to the data pin of the chip. This happens many times in parallel, on a number of chips, to produce a total number of bits corresponding to the width of the data bus.

    For writing, the new cell value is put on the data bus and, when the cell is selected using the /RAS and /CAS,it is stored in the cell. A pretty straightforward design! There are, in reality – obviously – many more complications. There need to be specifications for how much delay there is, after the signal, before the data will be available on the data bus for reading. Again, the capacitors do not 'unload' instantaneously, as described earlier... The signal from the cell is so weak that it needs to be amplified. For writing, it must be specified how long the data must be available on the bus after the /RAS and /CAS is done to successfully store the new value in the cell (again, capacitors do not fill or drain instantaneously). These timing constants are crucial for the performance of the DRAM chip!

    As mentioned, DRAM cells 'leak' their charges out over time, so that charge has to be refreshed if the DRAM is actually going to be useful as a storage device. Reading from or writing to a DRAM cell refreshes its charge, so the most common way of refreshing a DRAM is to read periodically from each cell. This isn't quite as bad as it sounds for a couple of reasons: first, you can sort of 'cheat' by only activating each row using //RAS, which is how refreshing is normally done; second, the DRAM controller takes care of scheduling the refreshes and making sure that they don't interfere with regular reads and writes. So to keep the data in DRAM chip from leaking away the DRAM controller periodically sweeps through all of the rows by cycling /RAS repeatedly and placing a series of row addresses on the address bus. A RAM grid is always a rectangle, and not a perfect square - you want fewer rows and more columns because the fewer rows you have, the less time it takes to refresh all the rows - hence the rectangular layout.


    You see, that for practical reasons, memory is 'presented to' the memory controller as a multi-dimensional array of cells ('bits'), somewhat like a spreadsheet containing many 'sheets' of rows by columns. The 'selection' of each dimension corresponds to a physical process - that is, itself, dependant on physical laws. A 'W' picofarad capacitor put across an 'X' volt supply with 'Y' resistance, takes 'Z' amount of time to 'charge' to 'X' volts! You can make it slower, but you can never make it any faster...

    We will not delve here (for brevity, which, BTW, I see I'm already not doing too good at[:isamuelson:6]!) into the further physical organization of these arrays: 'chips vs ranks/banks, 'sides', and how the on-DIMM memory controller physically 'handles' these elements - suffice it to say that there is low-level complexity, and at every step, each level takes real, physical time!

    What latency is, and why it matters:
    blah blah

  42. Memory - Part II

    Types of memory in your computer, and how they are used:
    blah blah

    How CPU cache, ISR's, and the 'thread manager' combine to make memory speed (mostly) irrelevant:

    There is a place where high speed, versus low latency, will be an advantage - any operations that require large, sustained, reads from and writes to RAM - like video transcoding... I always consider my 'pass/fail' system stress test to be: watch/pause one HDTV stream off a networked ATSC tuner, while recording a second stream off a PCIe NTSC tuner, while transcoding and 'de-commercialing' a third stream to an NAS media server... But, for the vast majority of people, for the vast majority of use, this is not the case. What is going on behind the scenes: the task scheduler is scurrying around, busier than a centipede learning to tap-dance, counting 'ticks': ...tick... yo - over there, you gotta finish up, your tick is over, push your environment, that's a good fella; oops - cache snoop says we've got an incoherency - grab me a page for him from over there; you - get me the address of the block being used by {F92BFB9B-59E9-4B65-8AA3-D004C26BA193}, will 'ya; yeah - UAC says he has permission - I dunno - we'll just have to trust him; damnit - everybody listen up, we've got a pending interrupt request, everyone drop what you're doing, and you - over there - query interrupt handler for a vector - this is important!!! ...tick.... And the most fascinating (scary) thing about it all, is that, at some synaptic, neural level, we're doin' the same thing! (...though, the older I get, the less dependable my interrupt return mechanism is - I repeatedly find myself at the bottom of the basement steps, wondering "now what did I come down here for?!")

    Why synthetic bechmarks are called 'synthetic'!
    blah blah
  43. I like the start of this new potential sticky. Looks like it will be a very interesting read. One formatting suggestion though (since I know my ME Lab graders would come after you for it): for the figure, move the description right up with where it says "Figure 2.4" and put "Figure 2.4" in bold. It will help make those who are just skimming for the pretty pics read some and realize what an informative post it is.
  44. GIGABYTEs and Memory - Part III - "Evaluation and selection"

    other content:
    GIGABYTEs and Memory - Part I - "What memory is"
    GIGABYTEs and Memory - Part II - "What memory does"
    GIGABYTEs and Memory - Part IV - "Tweaking and tuning"

    The difference between "Supported Speed", and "Supported Speed"!

    The board makers say "DDR3-XXXX Supported!!", meaning the circuitry on the board can be coaxed, one way or another, eventually, into making at least one piece of someone's XXXX speed memory function. They know that less than 1% of their customers have even a vague idea of what's actually involved, but more than 90% will be mightily impressed by 'BIG NUMBERS'! They simply can't pass by the marketing advantage to those big numbers...

    Then, there is the processor. Intel plainly states: DDR3-800, DDR3-1066, and, on some processors, DDR3-1333 are supported - and that's IT! I have pointed this out more than once:

    "Intel® Core™ i7 Processor Extreme Edition and Intel® Core™ i7 Processor Datasheet, Volume 2"
    2.14 Integrated Memory Controller Miscellaneous Registers

    2.14.1 MC_DIMM_CLK_RATIO_STATUS This register contains status information about DIMM clock ratio
    Device:3 Function:4 Offset:50h Access as Dword
    Bit 28:24 MAX_RATIO. Maximum ratio allowed by the part.
    Value = Qclk
    00000 = RSVD
    00110 = 800MHz
    01000 = 1066MHz
    01010 = 1333MHz

    Bit 4:0
    QCLK_RATIO. Current ratio of Qclk
    Value = Qclk.
    00000 = RSVD
    00110 = 800MHz
    01000 = 1066MHz
    01010 = 1333MHz

    2.14.2 MC_DIMM_CLK_RATIO This register is Requested DIMM clock ratio (Qclk), the data rate going to the DIMM. The clock sent to the DIMM is 1/2 of QCLK rate
    Device:3 Function:4 Offset:54h Access as Dword
    QCLK_RATIO. Requested ratio of Qclk/Bclk.
    00000 = RSVD
    00110 = 800MHz
    01000 = 1066MHz
    01010 = 1333MHz

    As Porky Pig used to say, at the end of every cartoon, "Th-Th-Th-!" Everything else falls under the broad label of 'undocumented' - like fifteenth century maps marked "here be dragons!" I'm not saying it can't work; it obviously does work, sometimes... Somehow, the BIOS and the board hardware are being manipulated to 'fool' the CPU into clocking the memory faster than spec - but it's one of those "pay no attention to that little man behind the curtain" things... AND: If you 'rob Peter to pay Paul' long enough, you wind up with a sore peter! :lol:

    Regarding "Intel Supported", there are major advantages to staying within these specifications. The i3/i5/i7 have 'moved' the memory controller onto the processor die. One of the reasons (among many) for the existence of the above mentioned memory configuration registers, is that the memory controller contains 'training' functions: much like the process of the BIOS 'waking up' the machine, and 'discovering' or 'polling' what devices are available, and how are they 'hooked up', the memory controller turns on, looks at its memory configuration registers, and attempts to 'hook up' to the physically attached RAM. The first thing it must do is determine the actual layout of the memory - the 'organization' by rows, columns, ranks, and sides that we discussed in section I. Then, it will attempt to 'adjust its ciruitry' to the physical characteristics of the RAM itself. It needs to 'measure' the impedance characteristics of the on-DIMM RAM controller chip, and the attached DRAM itself; in other words, the combined effects of resistance and capacitance (as well as any 'stray' inductance - a bad thing!) [from section I, again...], that will affect its physical transactions/speed...

    As the CPU has not got access to a multimeter, oscilloscope, or logic analyzer, it can only do this 'measuring' by 'looking at' two domains: voltage, and time. It sends a 'pulse' or command from here, and watches there, for a return; it says "Ah-ha! It took so long, to reach such voltage - I must adjust myself' thusly!" And, hopefully, your memory channels are as 'tuned' as they're going to get...

    Now, Intel specifies everything, and guarantees nothing! If your memory is constructed exactly to JEDEC spec, and the 'physical hookup' is done correctly, and the planets are in the proper alignment, 'training' will work... In numerous places, Intel's documents contain the 'electronic engineering equivalent' of "your mileage may vary!" This is where your "sore peter" comes in - if you're ridiculously outside Intel's physical specs (and, let's face it - 2166 memory is twice the 1066 supported by all i3/i5/i7 CPUs, meaning it requires the memory controller to perform its functions in half the time - which, patently, falls into the 'realm of the ridiculous'), you sacrifice any benefit of these 'built-in' accommodations!

    I consider myself a fair-to-middlin' amateur philosopher; and the great cognitive philosopher Daniel Dennet has written "one of the proper jobs of philosophers is definition mongering" - you can plainly see here that one person's definition of 'supported' (the board maker's and memory manufacturer's) varies wildly from another's (the processor manufacturer's)!!

    The GB 'Memory Support List', and how to use it:

    The support list is done when the board design is finalized to production, and almost never updated thereafter. When this is done, somebody with some degree of engineering talent, and knowledge of the hardware involved, sits down with a collection of RAM they have 'lying about', mostly samples provided by manufacturers who have a vested interest in getting their products on the list. He tosses aside the candidates he knows won't work, for one reason or another, on that particular platform, and goes to work setting up and testing the remainder. If he can get it working - it goes on the list; if not, not! I imagine he stays at it until he reaches some arbitrary number, or until his boss says "you got other, important work to do - GIT!"

    This leaves a large number of issues for the user:

    Being 'on the list' does not guarantee 'instant' compatibility for your use; the list provides no detail regarding "did it just come up and run with a 'Load Optimized?'', "did he have to enable XMP and it worked?", or, "did he (with 'inside' knowledge of the MOBO and BIOS) have to 'diddle around' a half-hour to set it up?"

    Not being on the list certainly does not imply it won't work! I have built a little Excel 'tool' for evalution and comparison of RAM; I went to update its contents just to reflect what's available in 2G x 3Channel from NewEgg, and, if memory serves me, wound up with eighty-some odd part numbers! Considering the ungodly amount of MOBOs GB makes, this would require a full-time staff of ten, even assuming the samples were consistently available - else another ten could work all day every day 'hunting down' samples! Your RAM part's absence may simply reflect that it was released after the board...

    Many parts you'll see on the list are from unfamiliar makers - they may be available in every quick-service gas-station in Taiwan, but simply aren't available in your market...

    The main advantage I see in 'sticking with' items on the memory supported list is just that - the position it puts you in, vis-a-vis GB support! If your memory can pass MemTesting a single stick at a time, and it is on the QVL, you have GB support pretty much 'over a barrel' - they have to help get the stuff running - they're the ones who said it would!

    In any other situation, you're pretty much trapped in what, unfortunately, has become an industry 'standard operating procedure' of 'passing the blame' - kind of like the Scarecrow in the Wizard of Oz crossing his arms across his chest, pointing in both directions, and saying "They usually go thataway!" The memory manufacturer says: "well, it must be your board, because that memory works at rated speed on 'ABC' board"; the board manufacturer says: "it must be your memory, because 'DEF' memory works on our board at that speed"; the CPU maker says: "it's your problem, because our CPU is rated to run RAM at 'GHI' speeds"; the software guys say: "it's obviously a hardware problem, because it works on 'UVW' platform; the hardware guys say: "it's obviously a software problem, because 'XYZ' program, which does the same thing, runs fine on our platform"; meanwhile, you are 'stuck in the middle', saying "'%$#&' these people, why can't somebody tell me how to make it work?!?"

    Evaluating memory from a price/performance standpoint:

    As discussed in part I, latencies are 'rated' in 'counts' of memory cycles, faster (smaller numbers) being better; and are, per part II, the most important factor in practical memory performance - this brings us to another (complicating) issue: Q - quick, which is better? A CAS latency of seven at DDR3-1066, or a CAS latency of nine at DDR3-1333? A - who the hell knows!?!

    No matter how math-phobic we are[:fixitbil:8], the actual answers are going to require some (not too serious) calculating. Bear in mind while trying [:fixitbil:5] to follow this: "Figures don't lie, but liars (and marketing guys!) figure." - Samuel Clemens (alias Mark Twain) One of the loosely kept 'secrets' in charging the 'big bucks' for (ostensibly and nominally) 'fast' memory is that almost no one knows the answers (or, more importantly - how to get them!) requisite to make these comparisons... Don't be put off by the math - I'm not going to expect you to do the math (heh-heh-heh, have a 'secret' still 'up my sleeve'), I just want to walk through the math, so you get an idea of the concepts involved in not wa$ting the money $pent on RAM!

    Again, to re-iterate: the latencies are physical periods of time, necessary to perform physical functions - functions that simply cannot be 'speeded up'! So, how do we go about finding the answer to the earlier question regarding comparison of latency numbers at differing speeds? Simply put, the latencies are some number of counts multiplied by some period of time, per count, at whatever given speed. The number of counts is easy - it's 'given' in the memory specifications. The period of time per count, is 'close to easy'; the period is the reciprocal of the frequency! (...don' sound easy put that way, does it[:fixitbil:4]?) Think of this: we have a sewing needle in a sewing machine that makes five strokes per second; how long does each stroke take? Obviously - one-fifth of a second, that is 1/5th second! Much easier, no? 'Period' is alway equal to one (the time unit - usually a second for 'electronics junk'), divided by the frequency (the number of occurences per unit of time)...

    When we are simply trying to get comparisons, the units of time really don't matter to us. You might remember, from science class (if you weren't 'sleeping through' that particular day - I couldn't sleep, was in Catholic school, with 'Sister Mary Attila' hovering around!), that 'scientific math numbers' are often presented in 'scientific notation', thusly: "1.36459 x 10 to the minus ninth" - beause it's easier than trying to keep track of: ".00000000136459"! At computer frequencies, time periods usually wind up being in microseconds (a millionth of a second, or ten to the minus sixth seconds - for really sloowww stuff), nanoseconds (billionths of a second, or ten to the minus ninth seconds - which most latencies are given in), or picoseconds (trillionths [one millionth of a millionth] of a second, or ten to the minus twelveth seconds - which might be the 'rise time' of a particular individual signal). So long as you are doing the same math the same way for a couple of closely-related frequencies, all you really care about is the "1.364" part of the "1.36459 x 10 to the minus ninth" answer!

    So, for calculation purposes, we're looking at a number of 'ticks' of the memory clock, times the length of each tick. For the earlier example, seven ticks at 1066 gives us: 7 x (1/1066), or 7 x 9.38e-4, which is 6.57e-3; nine ticks at 1333 gives us: 9 X (1/1333), or 9 X 7.50e-4, which is 6.75e-3; we can 'toss out' the units (powers of ten), and just look at the 'bare' numbers. 6.57 'somethingths' of a second is smaller than 6.75 'somethingths', so seven latency at 1066 is a teensy bit ('bout three percent) faster than nine latency at 1333!

    Another consideration you need to be aware of is the 'integer rounding' effect. As I've pointed out repeatedly, the latencies are actually physical time periods, for physical processes, usually given in nanoseconds. Integer rounding affects your memory thus: the nanosecond latencies are actually 'counted out' in 'memory clock ticks'; if you have a seven nanosecond latency, and your memory clock is 1066, the actual latency calculates to 7.46 'clocks', but you can't set 7.46 - you must always 'round up' to the next higher integer, in this case eight. Eight clocks at 1066 is seven and a half nanoseconds, which means you have to 'waste' a half nanosecond (or roughly 7%) each time the latency is activated - but that's simply how it works! This is an advantage for high speed memory; statistically, you are going to 'lose' a half-cycle on average, every transaction - faster (higher frequency) RAM has 'shorter' clock cycles, so that 'half-cycle' waste gets relatively smaller with each step's increase in clock speed...

    Now, you're probably saying "this guy is nuts, and he's gonna try to drive me crazy, too, if he thinks I'm gonna struggle through all this to pick out a couple lousy sticks of memory!" The 'secret' up my sleeve is:

  45. Memory - part IV - Making it work!

    Timings, 'sub-timings', and "why is this crap a secret?"
    blah blah

    Tweaking, testing, and tuning - practical techniques:
    blah blah blah

    MemTest Techniques:

    MemSet/CPU-Tweaker Technique:

    MemSet/CPU-Tweaker, EasyTune(X??), OverDrive, or BIOS: which should I use?

    This is a Genuine FIX, please DO NOT RETURN YOUR BELOVED RAM, as I was about to do. Please do not take this with a grain of salt, this will guarantee that your ram will be back to its original capacity. Please post THIS FIX to all the PEOPLE who are having this exact same problem with different ram & motherboards of the TRIPLE CHANNEL X58 variants.

    I have discovered luckily through thorough process of elimination that (keep in mind that I am not a techy, just very good with hardware... being that I can always source out the problem), when there is minute alterations to physical hardware while your PSU (voltage source is connected to your motherboard that the chipset or CPU's memory controller enters a SAFETY state or locks out certain physical hardware from damage, as personally I have discovered as I have a dual PSU setup with exactly 1000Watts. I had unplugged my 400watt PSU to try and fix my power led connector as the light wasn't on after I tried a ridiculous overclock attemp. Now to my understanding intel has hard coded a fail safe in the hardware (chipset or CPU) that when there is a very minute voltage fluctuation in voltage sensitive devices, I'm pretty certain that the QPI is the most vulnerable and sensitive part when it comes to voltages, as it communicates with the CPU at high bandwidth much like cache & at the same kind of voltage as the CPU (QPI is roughly 1.2volts = very small and sensitive voltage).


    You have to physically reset your system to re-instate your memory capacity, this is how it works... I'll put it in step form.

    STEP 1. Shut down & Power off your PC, physically at the PSU Power switch, or in my case switches.

    STEP 2. Remove all memory modules to discontinue any voltage source to QPI.

    STEP 3. Reset CMOS & reinstall modules.

    * In my case I had problems with both my inner & outside DIMM slots as they weren't working & only the inner slot worked (2gb of 6gb that I had was only running), so I tried to reset everything & just put one module in the first white DIMM slot (i have a Gigabyte X58-UD3R) & wallah she was working again!

    STEP 4. Put all modules back in & then power on the PSU.

    STEP 5. Power on your PC & jump into your BIOS & check your memory capacity.

    *To prevent memory reverting to reduced (2gb for your 6gb tri channel or 4gb of 12gb tri channel) you have to make certain that there are no physical voltage fluctuations, if by removing connected PCI Express connectors while the PSU is still on or trying some ridiculous overclock attemp. So please keep this in mind if you don't want to loose your precious overclock settings or to prevent any damage to your system.

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