What is the diefference?

[NNNN]

discuss alternatives of using a very large L2 cache versus a smaller L2 cache with an L3 cache. Discuss the arguments for each approach.

 

[TheDraac]

Damn... I was hoping to skip class today so I could miss this discussion.... LOL

 

[sighQ2]

hmmm - big topic, and over my head - but I am game for sitting in on the class.

I know that size looks good on a spec sheet; but there's a lot more to it. Stuff like prefetching, how long data stored, how data accessed, communication between L2 and L3, what prompts cache dumps. Also, the cache size is part of die size, which is about yield, and cost. It's all about overall architecture, and the bottom line is performance - does it really work. This is a call for a small course on design - or perhaps it's a test of the readership generally.

Usually this forum doesn't get into stuff like that - AMDzone does - some people over there are like gurus; but people here don't like the zone cos they bust myths about spintel benchmarketing etc. Zoners are written off as lunatics here. Some want to write me off for my preferences also. Fud to keep people down seems more important than truth. Not much talk of FTC and antitrust around here - or what do you support?

But a super tek discussion would be nice.

/echo - sounds like an assignment, doesn't it - or the final exam?

 

[welshmousepk]

it seems to me that a larger L2 cache would be of bigger benefit. im certaiunly no expert on the matter, but since the access time to L2 would be faster than that of l3 (right?) youd think the performance gains from more L2 would scale better, compared to L3.

but its also very important the L3 cache isnt too low, since in games this is the primary buffer for instructions (again, i THINK im on the right line here). so if the l3 is too low, performance will suffer regardless of how much L2 is available.

id like to see someone with the knowledge chip in though. im always up for some learning.

 

[cjl]

hmmm - big topic, and over my head - but I am game for sitting in on the class.

I know that size looks good on a spec sheet; but there's a lot more to it. Stuff like prefetching, how long data stored, how data accessed, communication between L2 and L3, what prompts cache dumps. Also, the cache size is part of die size, which is about yield, and cost. It's all about overall architecture, and the bottom line is performance - does it really work. This is a call for a small course on design - or perhaps it's a test of the readership generally.

Usually this forum doesn't get into stuff like that - AMDzone does - some people over there are like gurus; but people here don't like the zone cos they bust myths about spintel benchmarketing etc. Zoners are written off as lunatics here. Some want to write me off for my preferences also. Fud to keep people down seems more important than truth. Not much talk of FTC and antitrust around here - or what do you support?

But a super tek discussion would be nice.

/echo - sounds like an assignment, doesn't it - or the final exam?

People at AMDzone are clueless. I certainly wouldn't trust them for any sort of technical discussion of caching.

In general, L2 is faster. It also tends to consume more power and be more sensitive to defects, due to the higher clock speed. L3 is often run on a separate clock and power plane, hence it will run cooler. Because of this, you can often have more total cache if you add a L3, although this isn't always the case (as seen with the 12MB L2 Core 2 Quads).

 

[andy5174]

People at AMDzone are clueless. I certainly wouldn't trust them for any sort of technical discussion of caching.

In general, L2 is faster. It also tends to consume more power and be more sensitive to defects, due to the higher clock speed. L3 is often run on a separate clock and power plane, hence it will run cooler. Because of this, you can often have more total cache if you add a L3, although this isn't always the case (as seen with the 12MB L2 Core 2 Quads).

1. Strongly agree. Although I don't hate AMD and their customers, I DO hate those AMD fanboys at TOM who always deny the truth and make ridiculous opinions.

2. I didn't know that and was also wondering what the difference between L2 and L3 is. Great info!

 

[andy5174]

@ cjl:

Is L1 faster than L2?

 

[cjl]

1. Strongly agree. Although I don't hate AMD and their customers, I DO hate those AMD fanboys at TOM who always deny the truth and make ridiculous opinions.

2. I didn't know that and was also wondering what the difference between L2 and L3 is. Great info!

Note that the cache specifics depend very strongly on the specific design. I know the i7/i5 models use the separate power plane for L3, but I'm not positive about Phenom II (I'm pretty sure they do as well, but I'm not positive). L2 could be designed the same way as well if necessary, but it usually isn't for speed reasons. You could make a CPU with a large L1 and an L2 that was as slow as current L3s, and it would work fine. This isn't done due to the extremely tight tolerances on L1 (it is phenomenally fast and low latency), and a CPU designed like this would be quite expensive.

 

[cjl]

@ cjl:

Is L1 faster than L2?

Yep. They both are typically clocked the same as the CPU core clock, but L1 has significantly lower latency and higher bandwidth. L1 is the fastest memory (of any type) in a typical computer.

This is a decent overview:

http://en.wikipedia.org/wiki/CPU_cache#Cache_hierarchy_in_a_modern_processor

 

[andy5174]

It depends very strongly on the specific design. I know the i7/i5 models use the separate power plane for L3, but I'm not positive about Phenom II (I'm pretty sure they do as well, but I'm not positive). L2 could be designed the same way as well if necessary, but it usually isn't for speed reasons. You could make a CPU with a large L1 and an L2 that was as slow as current L3s, and it would work fine. This isn't done due to the extremely tight tolerances on L1 (it is phenomenally fast and low latency), and a CPU designed like this would be quite expensive.

Thank you!

 

[cjl]

Interestingly enough, that reply was to the post above the one it seemed to answer, since I didn't see your question until after I posted that. I tried to elaborate a little more in the post after that one.

 

[andy5174]

I was going to ask you where I can find articles about the cache. LOL

Thanks a lot.