I mention this briefly in the
'sticky', under the
Sorting Out SATA section:
Another often confused issue: the "Native Mode" setting for the SATA controller; unless you are one of the six people who ever
actually bought Windoze ME, you
always want this setting at "Enabled" - it turns
on interrupt sharing for the controller, and ME was the last version that did not support this...
To get a better 'grip', you might want to read
this earlier post about the interrupt mechanism itself, before proceeding...
Now that you've looked at the 'skirt-tugging' example, I'll explain a bit of 'evolution'. Back in 'ye olden days', this 'skirt tugging' was a pretty limited thing, as there wasn't all that much hardware to handle, and it wasn't going all that fast. The interrupts were individual, physical and electrical 'lines' into a single chip; this chip 'saw' an interrupt, and gave the CPU its own 'skirt tug' - a single line going high, along with a three bit (8 ID) 'code' saying
which interrupt had been 'hit'; this eight bit code then referenced a segment that stored, at startup, the 'jump vectors', or program addresses that
contained the service routines for each respective interrupt. When the IBM PC architecture began, this was too limited, as they had new-fangled 'slots' you could (wondrously) fill with you own 'junque', they added a second controller chip, 'piggy-backed' onto the first, and added a bit to the jump-vector table decode, so you knew
which chip went active. The interrupt lines were still dead-dumb hardware, however, set by fiddling with little jumpers (one per IRQ [interrupt request line], if your hardware was
really advanced; a coded pattern of three or four if it wasn't!), and you became (all too) familiar with your machine's interrupt architecture - as you'd run out! You wanted new piece of crap "X" for your machine, but it only supported interrupt "Y" or "Z", and, dammit, I got a modem on "Y", maybe I could move my parallel port from 7 to 5 - no, wait, that won't work either, 'cause I've got so-and-so
there, maybe I could... So, eventually, to get rid of the ton of constraints, and accommodate a flood of new hardware, they came out with PICs (
programmable
interrupt
controllers), that were more versatile, and could allow those harware lines to be 'shared', while still identifying the 'originating culprit', and lately, APICs, (
advanced
programmable
interrupt
controllers) who could do the same, and even handle multiple processor's responses...
Long story, but that's what this BIOS 'bit' is doing - it's telling the harware whether there's a 'shareable' PIC there - so the interrupts can be 'shared out'; this is faster (how much, I couldn't guess), more versatile, and less failure prone (same caveat), but the one thing I'm
not sure of is if an OS installed one way, will work properly once you've 'toggled' this setting - and the only way I can think of to find out - is to try it!
PS - BTW, this 'making your life simpler' comes at a cost: the interrupt mechanism, handlers, and exceptions comprise sixty-seven pages in 3A of the Intel S'ware Developer's manual, with another twenty-four devoted to 8086 emulation ('old-stuff' compatibilty) mode!!