I'm looking at both of these boards as possibilities for an i7 build. I'm curious about how bandwidth is handled when a slot has to share its bandwidth with another slot.
For example, on the X58A-UD5, if I have graphics cards on PCIEx16_1 and PCIEx16_2, no bandwidth needs to be shared. If I need more SATA III ports and add a SATA III expansion card to PCIEx8_2, then that card has to share 16 lanes with PCIEx16_2.
Is there a way to control how cards share the bandwidth? In other words, can I use the BIOS, or perhaps an option in Windows 7, to tell the motherboard to give the graphics card in PCIEx16_2 twelve lanes, and give the SATA card in PCIEx8_2 just four lanes (since that's all it would need). Is there any way to control how the bandwidth is split?
Also, in regard to UD5 versus UD7, the only difference I can see is that the UD7 boards have larger Northbridge and Southbridge heat sinks, perhaps as part of a setup for water cooling. So, what's the difference between UD5 and UD7 models?
Also on this board, I know the EX58-UD5 is a good board for installing Hackintosh. Does anyone know about the X58A-UD5 Hackintosh capabilities? Yes, i know, it should work, but I'm curious to see if someone here has actually tried this, and what you had to do to make it work.
I originall wrote most of this reagarding someone's P55A-UD6, but it's mostly applicable, and the concepts and illustrations will do...
PCIe hardware 'channels' are 'bifurcatable' (bifurcate simply means 'to split in half'...) - here's a picture from the 5520 (the Xeon equivalent of an X58) chipset datasheet:
This is done by soft 'strapping' registers, which can be set 'on the fly', but, in practice, aren't. If you have a sixteen lane channel, you can use it as two eights, or an eight and two fours, or an eight, a four, and four ones - but you can never have more than the original sixteen (duh!), and it always acts in even 'splits' (you can't have two sixes and a four!)... The other complication is that there is a seperation of 'physical' and 'electrical' PCIe specs; 'physical' is the slot size, length, and the number of little contact 'fingers' contained; 'electrical' is the actual 'lane width' available from the 'split'; the only rule here is that the physical must be at least as big as the electrical - i.e., a 'physical' sixteen can, say, be only eight 'electrically', but an 'electrical' sixteen must be contained in a full-length sixteen 'physical'...
The 'splits' have to be accommodated in hardware; i.e., the slots or lane designations have to be 'distributed' in wiring (traces on the MOBO...) - you have, say, three x16 slots sharing 32 lanes of PCIe; the 'switching' is then done by the BIOS, via 'polling' ("what are you, and how many lanes do you want?") and 'negotiation' ("well, there's three of you, so eight lanes is all you get!); this negotiation is part of the PCIe spec. That said, I have never seen a board which had any BIOS settings, beyond enabling/disabling things like STA3 and USB3 which 'use up' lanes, that affect this 'distribution' in any way - it's all done by the card's (device's) 'negotiation'!
Best place to fing out 'what's possible' is to look at the system 'Block Diagram', which for most GB MOBOs is found on page eight of the manual... Again, this is for a P55A-UD6, but, the principles apply:
In the system block diagram, the PCIe layout is detailed; some of your PCIe comes from the CPU itself (red), some from the IOH (P55-green); note, especially, the little printed or's:
Now, here is the board layout, with the same slots (and devices, in the case of the SATAs) similarly color-coded:
So you see, the PCIe1's, and the single 4, have nothing to do with the top two x16/2x8 'split'; if you were to disable the eSATAs, and leave the x1 slots empty, you could get a single x4 from the bottom slot; but as soon as you either enable the eSATAs, or plug anything into an x1 slot, that P55 'channel' 'degrades' into four x1's (which is all you need...)!!