ARM improvements include "logical step". Huh?

Errr can someone translate the second paragraph of the quote into standard English?
In our previous research of ARM based chip technology, we found that a company called Intrinsity was making a name for itself by accelerating ARM CPU designs while reducing power consumption. In July, Samsung announced an Intrinsity enhanced 1GHz ARM Cortex A8 processor called the Hummingbird which was to take on Qualcomm Snapdragon. Intrinsity accomplishes this by simplifying designs which make for smaller transistors which ultimately provides additional power savings.

The key to this and many other performance tricks is the type of logic gate Intrinsity uses: 1-of-n domino logic, or NDL, part of its suite of technologies called Fast14 (named after the atomic number of silicon). Russo says NDL can speed up a logical step by 40 to 60 percent. About a fifth of the A8’s functions are benefiting from it, he adds.
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    Hmm, I have no idea what "1-of-n" domino logic is, but ordinary domino logic combines the best features of synchronous logic and asynchronous logic (which is subject to race conditions and hence malfunctioning unless all possible logic paths are tested under all possible conditions, which rapidly becomes prohibitively expensive the more complex the circuitry gets). In domino logic you precharge all the logic gates on one clock edge and then let the gates switch as fast as possible on the other clock edge, where the output of one gate triggers the input of the next without any clock synchronization (which slows it down). Sort of like setting up a chain of dominoes (slow) and then letting them knock each other down (fast). The key to domino logic is that it is limited to a certain number of gate stages so that the race conditions can be evaluated & accounted for (i.e., sort of a limited asynch logic).

    However according to Bing search results :\


    This paper presents a 1-of-N Domino Logic (NDL) gate synthesis in-place optimization. NDL gates are a special class of domino gates where each NDL gate has N one-hot outputs. Thus, each NDL gate is treated as a multi-valued function that is N-valued.

    A special Multi-valued Decision Diagram (MDD) is used to represent the functionality of an NDL gate. The MDD has a one-to-one mapping to the control logic transistors in an NDL gate. This allows the MDD to use different variable orderings to optimize the area and timing of an NDL gate.

    The proposed synthesis approach is to try different NDL gate layouts to reduce the area of each gate. The approach uses the best result after running four different algorithms. The "best" is determined by a cost function that is presented in this paper.
    1-of-N Domino Logic Synthesis
    Craig M. Files

    International Workshop on Logic Synthesis, 2009


    In general, domino logic has higher speed and lower area than equivalent CMOS designs, but domino logic is susceptible to cross-talk noise and power consumption. Thus, domino logic circuits are often hand-designed, highly-specialized optimizations of critical timing paths.

    This paper presents a synthesis methodology for 1-of-N domino logic (NDL) gates. NDL gates have a lower switching factor than standard ``dual-rail'' domino logic gates, and thus, use less power. Special routing of 1-of-N signals reduces the effect of cross-talk noise. Plus, NDL gates are used in a multi-phase overlapping clocking scheme that reduces race conditions and clock skew.
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