Can someone please help me, next week I'm going to quit this module.
a) Consider a multi-cycle MIPS architecture. Assume there are 4 types of instructions supported by the architecture:
L-type (5 cycles), S-type (4 cycles), R-type (2 cycles), B-type (3 cycles)
If a program with 100 instructions containing different types in following ratio:
L-type (15), S-type (25), R-type (50), B-type (10).
i) Calculate the average instruction execution time in CPI (cycle per instruction) on an unpipelined processor; (8 marks)
ii) Calculate the average instruction execution time in CPI on a pipelined processor but with 0.1*cycle overhead; (8 marks)
iii) Ignoring any latency impact, calculate the theoretical speedup gained from pipelining; (8 marks)
iv) In some MIPS pipeline implementations, the length of pipestages would be the same. In order to calculate the speedup, define an expression of speedup as a function using the following:
- Tunpipelined: execution time for unpipelined units.
- Tpipestage(i): the execution time of each pipestage (i), which may vary depending on the instruction type.
- Tlatch: overhead time between pipestages.
(Speedup = ?) (8 marks)
Explain and discuss your expression using results from the above example. (8 marks)