Ok, so I've got a cheap/old motherboard* which only has 1x PCI-E 1.0 or 1.1 port, probably 1.0.
I've got a Radeon HD 6850 which is a PCI-E 2.1 card, but is backwards-compatible with PCI 1.0 or 1.1 ports (not sure if with both or just v1.1, but either way the card is working on my computer).
However, I noticed that I have a setting in my Bios to change the (only 1x) PCI-E port from the default and minimum 100MHZ to a maximum of 200MHZ [and every 1 point in between], which is, as far as what I read, the regular speed of a PCI-E 2.1 port.
And I was wondering if I should try testing this option (OCing PCI-E to 200MHZ) out to test for increased performance - that is performance closer to what it's designed for on a PCI-E 2.1 port. However is this at all risky for some reason? I mean can the PCI-E 1.0/1.1 port handle it? And it's only set to 100 MHZ by default because PCI-E 1.0/1.1 gear aren't generally designed for any higher speeds? (or is there something else to it which I should be aware )
if it was safe there would have been a bios update for the board and you would have had an easy option (AUTO) to switch between 1.x and 2.x
The industry-standard reference clock frequency used for devices supporting PCIe 1.1, 2.1 and 3.0 is 100 MHz (±300 ppm generated using an HCSL signal format). It is common for embedded processors, system controllers and SoC-based designs to use 100 MHz HCSL format as the reference clock for the PCIe bus interface circuitry.
Oh yeah, you guys are right about the bus-speed of all PCI-E (being 100MHZ only), I don't know where I got the idea of PCI 2.x having a higher bus-speed from.
100Mhz is the reference clock speed that is pumped into the controller logic. The controllers themselves have a PLL which control the IO rate. PCIe 1.x has a transfer rate of 2.5 GT/s (Giga transfers per second) and uses 8b/10b encoding. The encoding results in only 80% of the transmitted data being actual payload data, the rest is used to reduce errors and improve signal tracking. This results in 2.0 GT/s of actual payload data which comes out to 250 megabytes per second per lane. PCIe 2.0 increases this to 5.0GT/s with the same encoding scheme, resulting in 500 megabytes per second per lane. PCIe 3.0 increases this to 8.0GT/s but changes the encoding scheme from 8b/10b to 128b/130b, decreasing the transmission overhead from 20% to 1.5%. This results in just under a gigabyte per second per lane