Need help with pipelining

Consider a multi-cycle MIPS architecture. Assume there are 4 types of instructions supported by the architecture:
L-type (5 cycles), S-type (4 cycles), R-type (2 cycles), B-type (3 cycles)

If a program with 100 instructions containing different types in following ratio:
L-type (15), S-type (25), R-type (50), B-type (10).


From the above information, how would I calculate the average instruction execution time in CPI on a pipelined processor but with 0.1*cycle overhead;
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More about need pipelining
  1. Google "average instruction execution time in cpi" it's really answered so many places,
    and is part of basic computer architecture math. You'll find what you need.
  2. I tried, and found lots of theory, but don't know whow to apply it to this specific question. If you could help me, I would really appreciate it.
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