From the 22 nm article:
"The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point.
Since the 32 nm half-pitch already requires using double patterning, in conjunction with hyper-NA (numerical aperture) immersion lithography tools, this approach will continue to be used at the 22 nm half-pitch, to which it can be scaled."
All this techspeak tells you is how you get circuit elements smaller than the wave length of light you are working with.
To give you an idea of what they are working with, the gates at 32 are about 10 atoms thick.