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AMD to Redesign Memory Controller in Bulldozer Chips

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a c 161 à CPUs
a b À AMD
a c 163 } Memory
September 18, 2010 5:34:54 AM

Quote:
"There will be enhancements to our memory controllers, things we canot talk about just yet, that we expect to help reduce the time to access memory, both locally and remotely," said John Fruehe, John Fruehe, the director of product marketing for server/workstation products at AMD


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a b à CPUs
September 18, 2010 2:08:46 PM

LOL - pretty scanty details there :p .

Anyway, they would have to reduce latency some as Nehalem is faster than P2 (and I presume Xeons similarly faster than Optys). Since Sandy Bridge is something like 2/3rds the L3 latency of Lynnfield according to the AT preview, then to keep pace BD will also need an improvement there.
a c 117 à CPUs
a b À AMD
September 18, 2010 9:52:39 PM

It seems the rumahs have the BD IMC at 1866MHz.

And the worst kept secret on the internets is for each 10% you bump the NB speed latency is reduced 3-4% and bandwidth is increased 3-4% --- with 'enthusiasts' clocking 50%+ from stock 2000MHz.

So that gives a little headroom for a nice bump in performance if they harness what is (for the most part) on the table right now ...

!