A quick primer on Sandy Bridge

[saint19]

The other innovation of note in Sandy Bridge's front end is the addition of a cache for decoded micro-ops. Old-school CPU geeks may recognize this mechanism from a similar one, called the execution trace cache, used in the Pentium 4. Again, this provision is a nod to the fact that modern x86 processors don't execute CISC-style x86 instructions natively, preferring instead to translate them into their own internal instruction sets. The idea behind this new cache is to store instructions in the form of the processor's internal micro-ops, after they've been processed by the decoders, rather than storing them as x86 instructions. Doing so can reduce pressure on the decoders and, I believe, improve the chip's power efficiency in the process. Unlike the Pentium 4, Sandy Bridge retains robust decode logic that it can call on when needed, so the presence of a micro-op cache should be a straightforward win, with few to no performance trade-offs.

Source

More news from Sandy

 

[xaira]

bulldozer dual cores will squash sandy quads...i hope...LOL

nice find saint

 

[jimmysmitty]

I always knew that Netburst had offered some insight. Looks like I was right. SB will take a page from Pentium 4 in hopes of better performance.

 

[fazers_on_stun]

Not only should it be faster to just 'replay' the decoded micro-ops, but I read somewhere (probably AT article) that SB can power down the decoders during that time and save some juice and build up the thermal budget for turbo > TDP.

 

[LePhuronn]

There was nothing wrong with the design concepts of Pentium 4, it's just the implementation was atrocious.

SB could well be an interesting chip.