Bulldozer Releasing in q2 2011, and some more info

[yannifb]

Well heres the post from JF:
http://blogs.amd.com/work/2010/11/09/server-highlights-from-financial-analyst-day/

What i took note of the most were the facts that the 8 core BD chip has a smaller die size than the 6 core Thuban, the larger and faster l3 cache, better memory controller for 50% more throughput, and a 500 Mhz Turbo Core across all threads.

 

[jimmyzline]

Well heres the post from JF:
http://blogs.amd.com/work/2010/11/09/server-highlights-from-financial-analyst-day/

What i took note of the most were the facts that the 8 core BD chip has a smaller die size than the 6 core Thuban, the larger and faster l3 cache, better memory controller for 50% more throughput, and a 500 Mhz Turbo Core across all threads.

I'm clearing some desk room now. TB on all threads? Sweet!

 

[elel]

Just waiting on the low power notebook parts - will try to keep my atom running till then . . .

 

[4745454b]

What i took note of the most were the facts that the 8 core BD chip has a smaller die size than the 6 core Thuban

Probably because what makes up a "core" changes when you talk about BD. I'm still worried that not having as many FP cores is going to hurt them. As for everything else it reeks of marketing speak. Larger/faster L3/memory is nice. But if its not faster then SB then who really cares? Doesn't need to be faster as long as its competitive.

 

[jf-amd]

Actually, in 128-bit mode, we have 1 FP per core. Just like intel. When it comes to doing 256-bit AVX, we share resources. Just like intel. We combine 2 FPs, they combine an FP and INT pipelines to get there.

If we don't have "real cores" because we share, then neither does intel.

This "not real cores" argument is getting tired, it's not getting any traction and people realize that. Both AMD and Intel are getting creative to try to bring new technologies to market. Those that insist that technology changes will never get any innovation. Both companies are innovating and it is time to look forward, not backwards.

 

[Guest]

I was going to go out and snap up a Sandy Bridge platform once it becomes available in Jan...

Now AMD is saying bulldozer is coming out in Q2 I guess I will wait a bit more.

What I'm really waiting for is single thread performance number vs SB as most apps I use is still single thread. From what I see BD does have a chance to beat SB in multi thread apps but my impression is SB would still destroy BD in single thread performance...

The only reason I'm holding off till Q2 is that I've watch a tech interview on youtube with someone from AMD saying somehow you could "put more resources" to single thread app... This gives me hope for BD single thread performance and is a good enough reason to hold off until Q2

(putting more resources to single thread @2:30)

http://www.youtube.com/watch?v=wxbG2AmdMNY

 

[4745454b]

Actually, in 128-bit mode, we have 1 FP per core. Just like intel. When it comes to doing 256-bit AVX, we share resources. Just like intel. We combine 2 FPs, they combine an FP and INT pipelines to get there.

I don't understand, can you educate me please?

This "not real cores" argument is getting tired, it's not getting any traction and people realize that. Both AMD and Intel are getting creative to try to bring new technologies to market. Those that insist that technology changes will never get any innovation. Both companies are innovating and it is time to look forward, not backwards.

All I said was that the die size is smaller because of how a "core" is changed. You can have an 8 core BD be smaller then a 6 core K10 (?) because of the missing FP cores. And by no means do I think this is a bad idea. I do wonder in which cases this will hurt compared to the old chips. But I think this will end up being a great thing. More so once Fusion is working properly and all FP math will be passed to the GPU part of the chip.

I feel that very exciting times are coming. Once its all worked out that is.

 

[jf-amd]

Intel has a 128-bit FPU. When they have to do AVX, they steal the other 128-bit (to get to 256-bit) from the integer registers.

The FPUs are actually not the huge die savings, there is more about the front end. Current designs have 1 128-bit FPU per core, Bulldozer will have 1 128-bit FPU per core as well, so we have not reduced size based on FPU, we reduced size by the reduction in transistor size (45nm to 32nm) and the front end optimizations.

 

[4745454b]

Current designs have 1 128-bit FPU per Int core, Bulldozer will have 1 128-bit FPU per bulldozer core as well

Fixed? Thats what I mean by the reduction in the number of FP cores.

 

[elel]

Current designs have 1 128-bit FPU per Int core, Bulldozer will have 1 128-bit FPU per bulldozer core as well

Fixed? Thats what I mean by the reduction in the number of FP cores.

No - if you look at the diagrams, each half of a bulldozer core has its own 128 bit fpu, and they are right next to each other and so can be combined into a single 256 bit unit. So, depending on how it is working, bulldozer will have either (1) 128 bit FPU per 'small core' or (1) 256 bit FPU per 2 'small cores', the two small cores being the two parts of the larger unit which bulldozer is built of - I forget what it's called.

 

[jf-amd]

Magny Cours is a 12-core processor with 12 128-bit FPUs.

Interlagos is a 16-core processor with 16 128-bit FPUs.

that is a 33% increase in FP units and a 1:1 core to FPU ratio.

 

[4745454b]

So, depending on how it is working, bulldozer will have either (1) 128 bit FPU per 'small core' or (1) 256 bit FPU per 2 'small cores', the two small cores being the two parts of the larger unit which bulldozer is built of - I forget what it's called.

Thanks, that might be the education I needed. It at least makes some sense, and jives with what we have been hearing. So again, my question becomes how and/or when will this come back to bit AMD? Is most of the time spent working in 128bit and 256 is hardly ever used? I would imagine that most of the time is spent doing FP math. BTW, Intel won't have the problem of pulling a second unit to do 256bit as SB will have 256bit units.

http://electronicdesign.com/article/digital/intel_s_avx_scales_to_1024_bit_vector_math.aspx

 

[jf-amd]

FP can be either 128-bit (supported today with essentially all SW) or it can be 256-bit once the new platforms come out.

But to take advantage of 256-bit, your applications need to be recompiled.

In 128-bit mode:
SB = 8 128-bit FPUs
BD = 16 128-bit FPUs

In 256-bit mode:
SB = 8 256-bit FPUs
BD = 8 256-bit FPUs

So, actually, the thing that "comes back to bit(e)" someone is intel, on existing legacy code for future non-AVX code.

 

[4745454b]

In 128-bit mode:
SB = 8 128-bit FPUs
BD = 16 128-bit FPUs

16? An 8 "core" BD CPU will have 4BD modules. This means they will have 8 Int cores, and 8 128bit FP cores, or 4 256bit cores. Where do you pull 16cores from?

 

[jf-amd]

From a 16-core server product vs. their (top) 8-core server product.

Client SB will be 4 core, client BD will be 8 core, so cut all of those numbers in half, you net out the same.

 

[elel]

From a 16-core server product vs. their (top) 8-core server product.

Client SB will be 4 core, client BD will be 8 core, so cut all of those numbers in half, you net out the same.

Cool. Thanks for explaining!

 

[4745454b]

I got the feeling you were talking about server chips. Are you talking about a 1P, 2P, or 4P server? Without knowing how many packages you are plugging into the server its hard to figure out what your talking about. I certainly hope you are comparing the same number of packages, and not comparing a 2P BD to a 1P SB.

 

[jf-amd]

Processor to processor.

Our 16-core 2P product will compete with their 8-core 2P product. I always do apples to apples comparisons.

 

[4745454b]

So AMD is going to release an 8 BD module server CPU? 16int core and 16 128bit FP/8 256bit FP?

I wonder if Intel has found a way to "fuse" two 128bit calculations into a 256bit one, or in other words do two 128bit calc per tick. If they have then there is no advantage.

For the record I happen to love AMD. I'm sorry if I came off as someone who didn't I seriously hope AMD can get the performance crown, if even for just a bit.

 

[fazers_on_stun]

From a 16-core server product vs. their (top) 8-core server product.

Client SB will be 4 core, client BD will be 8 core, so cut all of those numbers in half, you net out the same.

JF, can you comment on some of the rumors going around that BD needs 2 clock cycles to perform a 256-bit AVX instruction, vs. Sandy Bridge's 1 clock cycle? If true, then it seems to me BD's throughput will be around half that of SB.

 

[jf-amd]

So AMD is going to release an 8 BD module server CPU? 16int core and 16 128bit FP/8 256bit FP?

I wonder if Intel has found a way to "fuse" two 128bit calculations into a 256bit one, or in other words do two 128bit calc per tick. If they have then there is no advantage.

For the record I happen to love AMD. I'm sorry if I came off as someone who didn't I seriously hope AMD can get the performance crown, if even for just a bit.

No. the only way to do that is with AVX, which is how both of us are getting to 256. They don't have the registers to do that in 128-bit mode because both 128-bit executions would be looking for the same ports.

That is the whole idea behind AVX and 256-bit FP.

 

[yannifb]

I think that for the client side, BD will be amazing for gaming. Like JF mentioned in one of his blogs, when a program doesnt use all of the integer cores, a single module can act as a more powerful core, which is good for games that only use up to 4 threads (since the client BD will have 4 modules). As for games that do use 8 cores, BD will also shine i think. Plus since games are mostly integer (i think) that helps.

 

[V-Key]

I still feel torn. I am trying to decide whether to just go for the intel i7 now during black Friday or wait for the AMD bulldozer. There are no specs to compare performance vs the hex-core intel. And there was a comparison of the AMD hex core to the intel quad core, where intel still slightly outperformed AMD. Does anyone know about any expected performance difference vs their current chips?

 

[4745454b]

We can guess, but its really just a guess. We know more about the performance of SB then BD. We know some things about BD, but there is so much we don't know that effects the performance of the chip that it could go either way. I personally believe that it will be better then the PhII, but not quite enough to catch SD on the high end.

 

[V-Key]

Magny Cours is a 12-core processor with 12 128-bit FPUs.

Interlagos is a 16-core processor with 16 128-bit FPUs.

that is a 33% increase in FP units and a 1:1 core to FPU ratio.

So do you have any figures for performance increase vs the current Phenom II x6 ? And any idea about price range for the high end processor to compete with the i7's performance?