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About L2 and L3 Cache

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  • CPUs
  • Cache
  • Processors
  • Memory
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January 12, 2011 8:08:04 PM

Hello Everybody ,

Please, I have a question if you don't mind.

When I was studying in some technical material I read that the cache memory divided to internal and external memory. Usually L1 is an internal cache and it's located inside the processor package itself and L2 cache is an external cache and it's located in the motherboard.
When L3 cache arrived, the L1 and L2 cache consider as internal cache and L3 cache is the external memory.

Now if that information is true , could anyone explain that for me? and Where that external cache is located in the motherboard?
I always consider the cache memory is a property of the processor itself. Also I read in any processor specification that L1 ,L2 and L3 cache is determined by the processor.

please, help me.

thanks in advance :) 

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January 12, 2011 8:13:53 PM

You were reading an older book, my computer architecture textbook lists like 6 levels of cache and their speed from L1 on chip cache out to tape drive backups, but really they are sorted in order from closest to farthest, my book had the ram listed is L3, so take those charts in computer architecture books with a grain of salt, the idea is right, but the labeling was out dated by the time they printed it, mine came with a label below stating "Due to the rate computers advance this information is likely already outdated"

Older boards used to have L1 on chip, and SRAM chips around the CPU socket to serve as L2 cache, then they got moved onto chip, so we had L1 and L2 on the CPU, then they wanted more cache so they put L3 cache on the chip as well, much larger than L1 or L2, and significantly slower than L2 but still a ton faster than going to RAM.

Current processors like the Intel Core i series and the AMD Phenom II and Athlon II chips have the L1, L2, and L3 cache built into the CPU die, L3 tends to be shared among all cores, while L1 and L2 are dedicated to each core, so in this picture the L1 and the L2 cache exist within the parts labeled core
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January 12, 2011 9:39:54 PM

Aha I see,

The book I was read is " Sybex A+ Complete Study Guide " And it was printed in 2009 , so it's not that old I think.
Anyway thank you for your reply :) 
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January 12, 2011 10:55:40 PM

T3V4 said:
Aha I see,

The book I was read is " Sybex A+ Complete Study Guide " And it was printed in 2009 , so it's not that old I think.
Anyway thank you for your reply :) 


hunter315 was right, don't go by print dates :) 
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January 13, 2011 8:55:00 AM

akula2 said:
hunter315 was right, don't go by print dates :) 


OK I will be careful next time. Thanks:) 

So can you advise me on which book is good to study A+?
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a c 217 à CPUs
a b } Memory
January 13, 2011 12:36:47 PM

Wikipedia is probably the most accurate and up to date source you will find. I would stick with the book you currently have but if you hit something that seems a little off check on wikipedia, you can probably figure out where in the timeline your book got its stuff from and what is currently true.
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January 13, 2011 1:14:26 PM

@T3V4

Honestly I don't know much about A+ course because my path for acquiring the knowledge was different. When I was about to complete my 7th grade in 1985, started learning about Computers and a few languages (fell in love with 'C' and its printf() function!) on my first PC in my life - a 16-bit IBM 80286 machine. Later in my life, got into Engineering and earned a PhD in the process of getting the expertise in Electronics/Computers. I do specialize in Digital Signal Processing and Embedded Systems. Anyway, from the practical point of view I would certainly suggest these good books:

1) Bigelow's Troubleshooting, Maintaining & Repairing PCs with CD. I remember it as 5th Edition.
2) Upgrading and Repairing PCs with DVD by Scott Mueller (19th Ed./2010)

Note: 1st book is all about to get a good foundation about PC Hardware and the 2nd one branches above it with more relevant/latest information. Example, a Nehalem processor. Make sure you check for the latest edition.

You may also refer Wiki but I don't really rely on it from the accuracy, substance and depth point of view. But, it's quite a good reference for free. Anyway, let me know if you have any more questions and Good luck!
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a c 102 à CPUs
January 13, 2011 1:15:28 PM

T3V4 said:
Hello Everybody ,

Please, I have a question if you don't mind.

When I was studying in some technical material I read that the cache memory divided to internal and external memory. Usually L1 is an internal cache and it's located inside the processor package itself and L2 cache is an external cache and it's located in the motherboard.
When L3 cache arrived, the L1 and L2 cache consider as internal cache and L3 cache is the external memory.

Now if that information is true , could anyone explain that for me? and Where that external cache is located in the motherboard?
I always consider the cache memory is a property of the processor itself. Also I read in any processor specification that L1 ,L2 and L3 cache is determined by the processor.

please, help me.

thanks in advance :) 


The gist of cache levels are that the lower-level caches are "closer" to the core hardware and are accessible in fewer clock cycles than higher-level caches, but the higher-level caches tend to be much larger. The exact implementation of cache is processor-dependent as you state, but your book's information is pretty out of date. Today, anything referred to as processor cache is integrated onto the CPU die and motherboard-based caches are not present in any new x86 systems that I am aware of. All caches were external to the CPU prior to the 80486, which integrated an L1 cache into the CPU. External caches sat somewhere on the motherboard, often close to the CPU socket or the memory slots. L2 cache arose during the 486 days as the 486 had onboard L1 cache. The L2 cache also sat on the motherboard and ran at the FSB speed like the L1 cache did prior to the 486. This on-motherboard L2 worked okay until CPUs' core clock speeds started to rise disproportionately compared to the FSB and RAM speeds. Then the L2 cache was moved to a daughter card that held the CPU in the Slot 1/2/A cartridges so that the L2 cache could run at a higher speed than the FSB to yield better performance. Finally around the year 2000, it was possible to put the L2 cache on the CPU die itself and run it at the same speed as the core, greatly boosting performance compared to the off-die L2 caches. The integration of L2 cache onto the CPU die pretty well marked the end of motherboard-based caches. L3 caches were first seen used with x86 CPUs with the AMD K6-III. The K6-III was the first Socket 7 CPU with on-die L2 cache, so if your Socket 7 motherboard had cache, it became L3 cache when you plugged in a K6-III. Intel followed up soon after that with putting L3 cache on a CPU die with the first Pentium 4-based quad-CPU-capable Xeon, the Foster MP. Between 2001 and 2007, L3 cache was pretty much only used in Intel's 4-way server CPUs as the L3 cache helped to ameliorate bus congestion with their shared FSB design. L3 caches on consumer CPUs didn't become common until CPUs with four cores on one die were introduced in 2007, and most quad-core and all six-core or higher x86 CPUs have an L3 cache.

The only time you would see motherboard-based cache memory, whether it was called an L* cache or not, was in some servers with an FSB and four or more CPU dies. IBM's X3 chipset for 2002 and 2003's "Gallatin" Xeon MPs had some cache in the chipset called AccelL4, and Intel's 5000, 5400, and 7300 series Xeon chipsets had something like 64 MB of cache memory in the chipset, although Intel didn't call it by any cache level. The current CPU design with an on-die memory controller has completely eliminated motherboard-based cache levels.

The current usage of named cache levels in x86 CPUs is roughly the following:

- L1 cache: the smallest cache level. These are split into separate caches for instructions and data, and they are accessible in 2-3 clock cycles. There are separate L1 caches for each CPU core. L1 caches are somewhere in the neighborhood of 16-64 KB for each of the instruction and data caches.
- L2 cache: implementation varies a lot by CPU, although these are typically 256 KB-1 MB in size in current x86 CPUs and hold both instructions and data. The Core 2 generation has one large (1 MB-6 MB) L2 cache for two CPU cores and the two cores use this to communicate between each other. Other multicore CPUs have individual L2 caches attached to each CPU and the CPUs communicate via a crossbar or ring bus instead of the L2 cache. Latencies are roughly 10-12 clock cycles.
- L3 cache: this is the highest-level cache seen on current x86 CPUs and there is typically one L3 cache per CPU die and all CPU cores can access this data. Latencies are in the dozens of clock cycles and these caches are several megabytes in current x86 CPUs, although not all new x86 CPUs have an L3 cache. The Intel Atom, AMD Sempron, AMD Athlon II, and all of AMD's mobile chips have no L3 cache.
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January 13, 2011 8:56:12 PM

akula2 said:
@T3V4

Honestly I don't know much about A+ course because my path for acquiring the knowledge was different. When I was about to complete my 7th grade in 1985, started learning about Computers and a few languages (fell in love with 'C' and its printf() function!) on my first PC in my life - a 16-bit IBM 80286 machine. Later in my life, got into Engineering and earned a PhD in the process of getting the expertise in Electronics/Computers. I do specialize in Digital Signal Processing and Embedded Systems. Anyway, from the practical point of view I would certainly suggest these good books:

1) Bigelow's Troubleshooting, Maintaining & Repairing PCs with CD. I remember it as 5th Edition.
2) Upgrading and Repairing PCs with DVD by Scott Mueller (19th Ed./2010)

Note: 1st book is all about to get a good foundation about PC Hardware and the 2nd one branches above it with more relevant/latest information. Example, a Nehalem processor. Make sure you check for the latest edition.

You may also refer Wiki but I don't really rely on it from the accuracy, substance and depth point of view. But, it's quite a good reference for free. Anyway, let me know if you have any more questions and Good luck!


Thanks for your advice.
I'll try to find those books right here.
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January 13, 2011 9:06:09 PM

MU_Engineer said:
The gist of cache levels are that the lower-level caches are "closer" to the core hardware and are accessible in fewer clock cycles than higher-level caches, but the higher-level caches tend to be much larger. The exact implementation of cache is processor-dependent as you state, but your book's information is pretty out of date. Today, anything referred to as processor cache is integrated onto the CPU die and motherboard-based caches are not present in any new x86 systems that I am aware of. All caches were external to the CPU prior to the 80486, which integrated an L1 cache into the CPU. External caches sat somewhere on the motherboard, often close to the CPU socket or the memory slots. L2 cache arose during the 486 days as the 486 had onboard L1 cache. The L2 cache also sat on the motherboard and ran at the FSB speed like the L1 cache did prior to the 486. This on-motherboard L2 worked okay until CPUs' core clock speeds started to rise disproportionately compared to the FSB and RAM speeds. Then the L2 cache was moved to a daughter card that held the CPU in the Slot 1/2/A cartridges so that the L2 cache could run at a higher speed than the FSB to yield better performance. Finally around the year 2000, it was possible to put the L2 cache on the CPU die itself and run it at the same speed as the core, greatly boosting performance compared to the off-die L2 caches. The integration of L2 cache onto the CPU die pretty well marked the end of motherboard-based caches. L3 caches were first seen used with x86 CPUs with the AMD K6-III. The K6-III was the first Socket 7 CPU with on-die L2 cache, so if your Socket 7 motherboard had cache, it became L3 cache when you plugged in a K6-III. Intel followed up soon after that with putting L3 cache on a CPU die with the first Pentium 4-based quad-CPU-capable Xeon, the Foster MP. Between 2001 and 2007, L3 cache was pretty much only used in Intel's 4-way server CPUs as the L3 cache helped to ameliorate bus congestion with their shared FSB design. L3 caches on consumer CPUs didn't become common until CPUs with four cores on one die were introduced in 2007, and most quad-core and all six-core or higher x86 CPUs have an L3 cache.

The only time you would see motherboard-based cache memory, whether it was called an L* cache or not, was in some servers with an FSB and four or more CPU dies. IBM's X3 chipset for 2002 and 2003's "Gallatin" Xeon MPs had some cache in the chipset called AccelL4, and Intel's 5000, 5400, and 7300 series Xeon chipsets had something like 64 MB of cache memory in the chipset, although Intel didn't call it by any cache level. The current CPU design with an on-die memory controller has completely eliminated motherboard-based cache levels.

The current usage of named cache levels in x86 CPUs is roughly the following:

- L1 cache: the smallest cache level. These are split into separate caches for instructions and data, and they are accessible in 2-3 clock cycles. There are separate L1 caches for each CPU core. L1 caches are somewhere in the neighborhood of 16-64 KB for each of the instruction and data caches.
- L2 cache: implementation varies a lot by CPU, although these are typically 256 KB-1 MB in size in current x86 CPUs and hold both instructions and data. The Core 2 generation has one large (1 MB-6 MB) L2 cache for two CPU cores and the two cores use this to communicate between each other. Other multicore CPUs have individual L2 caches attached to each CPU and the CPUs communicate via a crossbar or ring bus instead of the L2 cache. Latencies are roughly 10-12 clock cycles.
- L3 cache: this is the highest-level cache seen on current x86 CPUs and there is typically one L3 cache per CPU die and all CPU cores can access this data. Latencies are in the dozens of clock cycles and these caches are several megabytes in current x86 CPUs, although not all new x86 CPUs have an L3 cache. The Intel Atom, AMD Sempron, AMD Athlon II, and all of AMD's mobile chips have no L3 cache.


You make it clear now.really thanks a lot.
The thing makes my confused that when I search on the Internet I found many sites say the same words, so I decide to ask you here because I can't accept that.

Thank you all guys :) 
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January 13, 2011 9:07:43 PM

Best answer selected by T3V4.
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