amdfangirl :
It's highly likely to be false given that how long it is before the product launch.
Not necessarily so (and maybe John can help us with this).
AMD has teams of engineers pounding away on microcode to repair errata, improve efficiency of instructions, etc., to optimize, enhance or even add new functionality. With the new design this becomes even more critical for AMD as they ramp to production. No real reason to 'spill the beans' as they continue to optimize before production, right?
There is an inherent "double-whammy" in this round: new design AND new instructions. This is not necessarily a bad thing.
My understanding (always questionable
) is a primary result of the AMD/Intel legal wranglings is 'Chipzilla' must be more forthcoming on future instruction sets. In the past Intel would not divulge this information until a microprocessor was physically on the retail market -- keeping AMD months (if not years) behind the curve. What's the big deal you ask?
Instruction set optimizations are both backward- and forward-looking. We want 'old' software already implemented to perform better, and we want 'new' software to 'scale' with future instructions. Is this making sense?
The history of the 'Chip Wars' are full of examples -- the latest being SSE4. With Penryn/Nehalem Intel brought forth dozens of 'optimized' SIMD instructions: SSE4, SSE4.1 & SSE4.2. Being behind the curve, AMD brought forth their own 'unique' SSE4
a instructions -- all three of them (being a 'Southern' American we would normally preface this with "Bless their heart" - LOL - just kidding, John!).
Guess what? Bulldozer will universally support almost all SSE4, SSE4.1 & SSE4.2 instructions, in addition to the new AVX instructions PLUS their own AMD "Instructions formally known as SSE5" (and now commonly referred to as XOP and FMA4).
And most importantly (the reason that AMD is so exceptionally tight-lipped about things these days): Randy Allen
Randy was doing his job a few years ago, and managed to stick both his feet into his mouth. He took a single unique instance of performance gains, and fairly or not, it was somehow implied as 'across the board' performance gains.
Bless his heart!