Okay, I was just looking at the cpu-z page for my computer. I noticed that under "clocks" there was something called the "Bus Speed". What bus speed is it talking about? It can't be the hyper transport bus, thats all ready listed. I am pretty new to building, so I appreciate your patience. Thanks so much!
Here is a picture of my cpu's CPU-Z
It isn't mine, I just pulled it off Google, but it is the same thing.
TheScorpion: that's a Phenom II, it doesn't have an FSB
McLizard: I believe that's just the base clock. There's no data transfer going on at that speed, it's just a reference clock for the core and possibly the HT bus as well (which is the thing that's listed as 2006.8 MHz just below it).
That makes enough sense. Why is it called the bus speed though? Also, I have a question about the memory bus, being the bus between the cpu and the ram, ar the northbridge and the ram. Do transfers between those two use the speed of the ram, say 800 mhz if it is 800mhz ram?
The huge difference between the internal clock and the external clock on modern CPUs is one major roadblock to overcome in order to increase the computer performance. Continuing the Pentium 4 3.4 GHz example, it has to reduce its speed by 17x when it has to read data from RAM memory! During this process, it works as if it were a 200 MHz CPU!
The bus speed (back when they used a bus) determines how many transfers per second that a processor can make between the northbridge and the CPU. The processor internal clock determines how many operations per second a processor can make on that data. The problem with this statement here is that it's assuming that in order to do one operation, you need one transfer's worth of data. This isn't really true. A processor is limited severely when it has to go to RAM, but not as severely as this statement would imply.
Several techniques are used to minimize the impact of this clock difference. One of them is the use of a memory cache inside the CPU. Another one is transferring more than one data chunk per clock cycle. Processors from both AMD and Intel use this feature, but while AMD CPUs transfer two data per clock cycle, Intel CPUs transfer four data per clock cycle.
This is now talking about dual pumped and quad pumped FSBs. It's interesting, but irrelevant, since both AMD and Intel use separate IMCs and high speed data links to the northbridge now, rather than a single FSB.
Because of that, AMD CPUs are listed as having the double of their real external clocks. For example, an AMD CPU with a 200 MHz external clock is listed as 400 MHz. The same happens with Intel CPUs: an Intel CPU with a 200 MHz external clock is listed as having an 800 MHz external clock.
Once again, outdated info (and not at all relevant to the OP's PhII)
The technique of transferring two data per clock cycle is called DDR (Dual Data Rate), while the technique of transferring four data per clock cycle is called QDR (Quad Data Rate).