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| 4745454b wrote : And I was going to seriously ask if we are allowed to post our own personal "theories" on SB/IB or if we have to find it in an article. |
4745454b: I would focus on articles you come across on the subject matter versus your own personal "theories", unless you have information to backup your "theories" 
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Reply to tecmo34
I kinda of like the way intel does its business.Its like the improvements are in increments.Even though some might find it strange.But it spreads out its product and gives us more choices.
And if Sandy bridge come cheaper cuz of ivy bridge every1 would have one by next year.
Message edited by ghnader hsmithot on 04-29-2011 at 06:53:38 PM
Here is some information I've come across (Unofficial - Official )
- Sandy Bridge-E is scheduled to be released in Q4 (looks to be early Q4'11).
- Ivy Bridge, which is the 22nm die shrink, will be released in Q1'12.
- Z68 chipset should be able to use Ivy Bridge with only a bio update.
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Reply to tecmo34
Some good stuff there guys and the links are a good read.
Keep up the good work !!
Reply to REYNOD
| ghnader hsmithot wrote : some z68 boards have come out already in China market.
|
Good to know - I'm waiting on Newegg to get some Asus or Gigabyte Z68 boards in, or else I'll drive the half-hour to Microcenter where I can get the 2600K for $279 .
^ Sounds like Intel is planning something big. Guess I'll check DailyTech later today to see what they had to say - otherwise stay tuned to THG next month for the news flash 
..
| ghnader hsmithot wrote : I am a bit doubtful of this technology.I hope it gives us more performance.Just doubtful of the problems. |
Well the problem with ever-shrinking process nodes is that the leakage currents tend to rise rapidly as a percentage of all currents. For example, at 45nm the leakage between the gate and the channel in a FET is significant, despite the fact that the insulator (SiO2) is basically pure glass. When that layer of glass is mere nanometers in thickness, even a ~1V potential difference between the gate and the channel will cause a significant amount of charge leakage. That current multiplied by the potential difference is just wasted energy that shows up as heat. Which is why Intel introduced HKMG that reduces the leakage signficantly, and which Global Foundries is now using at 32nm.
Another even bigger problem is the channel leakage - the residual current between source and drain - when the transistor is supposed to be OFF. Transistors are not really ideal ON/OFF switches - they alternate between mostly ON and mostly OFF, which means they waste power in either state, plus the parasitic capacitances cause them to waste energy when switching from one state to the other. Eventually as the process shrinks, more energy is wasted than actually used in performing useful computations, and that wasted energy shows up as unwanted heat. AMD uses Silicon-On-Insulator (SOI) wafers which greatly reduces the parasitic capacitance, at least at the larger nodes like 90nm, probably does not have as significant a benefit at the smaller nodes, because the above leakage currents start to outweigh the parasitic effects.
Tri-gate FinFETS reduce the channel leakage by a huge amount, relatively speaking, since now the charge carrier (electrons in N-channel FETs, holes in P-channel) now have to get past 3 potential barriers vs. one when the transistor is nominally "OFF". If each barrier gives an exponential tail-off, then the total leakage current will be significantly reduced.
Or at least that's how I imagine it works, given that I had solid-state physics and design some 20+ years ago ...
| fazers_on_stun wrote : Well the problem with ever-shrinking process nodes is that the leakage currents tend to rise rapidly as a percentage of all currents. For example, at 45nm the leakage between the gate and the channel in a FET is significant, despite the fact that the insulator (SiO2) is basically pure glass. When that layer of glass is mere nanometers in thickness, even a ~1V potential difference between the gate and the channel will cause a significant amount of charge leakage. That current multiplied by the potential difference is just wasted energy that shows up as heat. Which is why Intel introduced HKMG that reduces the leakage signficantly, and which Global Foundries is now using at 32nm. Another even bigger problem is the channel leakage - the residual current between source and drain - when the transistor is supposed to be OFF. Transistors are not really ideal ON/OFF switches - they alternate between mostly ON and mostly OFF, which means they waste power in either state, plus the parasitic capacitances cause them to waste energy when switching from one state to the other. Eventually as the process shrinks, more energy is wasted than actually used in performing useful computations, and that wasted energy shows up as unwanted heat. AMD uses Silicon-On-Insulator (SOI) wafers which greatly reduces the parasitic capacitance, at least at the larger nodes like 90nm, probably does not have as significant a benefit at the smaller nodes, because the above leakage currents start to outweigh the parasitic effects. Tri-gate FinFETS reduce the channel leakage by a huge amount, relatively speaking, since now the charge carrier (electrons in N-channel FETs, holes in P-channel) now have to get past 3 potential barriers vs. one when the transistor is nominally "OFF". If each barrier gives an exponential tail-off, then the total leakage current will be significantly reduced. Or at least that's how I imagine it works, given that I had solid-state physics and design some 20+ years ago |
Message edited by ghnader hsmithot on 05-05-2011 at 10:30:14 AM
fazers (or anyone): What about the actual "size" of the electrons in a 22nm circuit? Are we not getting to the point where we're looking at boulders hurtling down a pipe... but in this case boulders which have the nasty habit of materializing on the other side of a fixed barrier? Is it logical to assume that we've shrunk the process just about as much as can be expected before the LHC forces us to rewrite quantum physics?
| halfcalf wrote : fazers (or anyone): What about the actual "size" of the electrons in a 22nm circuit? Are we not getting to the point where we're looking at boulders hurtling down a pipe... but in this case boulders which have the nasty habit of materializing on the other side of a fixed barrier? Is it logical to assume that we've shrunk the process just about as much as can be expected before the LHC forces us to rewrite quantum physics? |
Eventually that will happen. There will be some manufacturing nightmares, but sooner or later, the design guys will see that there is life beyond La_La_Land! That's when it will hit the fan!
Reply to Ubrales
Ubrales & zulfadhli: Yeah, no matter how nano the technology, "ye canna change the laws of physics" to quote Lt. Montgomery Scott. What makes it especially interesting is that although I am in my 50s and have been around the scientific block at least a few times, I still have never read an explanation of electricity that (were it to describe anything else) would pass muster in any high school!
| halfcalf wrote : Ubrales & zulfadhli: Yeah, no matter how nano the technology, "ye canna change the laws of physics" to quote Lt. Montgomery Scott. What makes it especially interesting is that although I am in my 50s and have been around the scientific block at least a few times, I still have never read an explanation of electricity that (were it to describe anything else) would pass muster in any high school! |
The tragedy of science is the slaying of a beautiful hypothesis by an ugly fact!
Reply to Ubrales
| Ubrales wrote : The tragedy of science is the slaying of a beautiful hypothesis by an ugly fact! |
I agree fully. I still can't keep a straight face when somebody is yakking on about "electron flow" (really??? electrons flow, huh???) and the propagation as both a wave and a particle. That one is a knee slapper.
| halfcalf wrote : fazers (or anyone): What about the actual "size" of the electrons in a 22nm circuit? Are we not getting to the point where we're looking at boulders hurtling down a pipe... but in this case boulders which have the nasty habit of materializing on the other side of a fixed barrier? Is it logical to assume that we've shrunk the process just about as much as can be expected before the LHC forces us to rewrite quantum physics? |
Atomic sizes range from 0.3 to 3 angstroms in radius, an angstrom being 10^-10 meters or 0.1 nm. So that's 0.06 nm to 0.6 nm in diameter. I've seen some patents (Hitachi?? Don't recall the assignee) on single-atom "circuits", based on using scanning tunnelling electron microscopes that 'pick up' individual atoms and deposit them on a substrate, in which the Van der Waals force holds them in place. So basically you can make a line of atoms that are close enough together that single electrons can 'hop' from one atom to the next. IIRC it was IBM that showed how this could be done, back in the '80s when they wrote the company name "IBM" with helium (?) atoms on a nickel substrate.
The physics behind it are beyond me - when I was in college studying solid-state physics, the equations were based on bulk semiconductor properties where surface effects were negligible. So calculating band-gaps, etc was relatively easy using bulk properties. When you line up atoms on a substrate, it's all surface effects..
Anyway, the point of the patent was that you could make NAND and NOR gates and even memory circuits using single atoms lined up appropriately in circuits, using strongly-held atoms and loosely-held atoms (lesser Van der Waals attraction to the substrate), and these 'circuits' would be < 1 nm.
Of course, it would take probably a thousand years just to assemble a one-billion-circuit CPU, using SEM equipment and moving one atom at a time . But it would be 1/(22^2) times smaller than Ivy Bridge, and probably cost 2^22 times as much as Ivy Bridge .
fazers: If you say that the physics are beyond you then I have to say that I can't count to 21 without being naked. So I certainly can't add to your superb analysis. It would seem to me (with my junior ankle biter grasp of the issue) that the single atom layer graphene experiments might end up being used in some way for this hopalong scenario. That would create exactly what I'm looking for: A CPU that costs more than the Obama deficit.
zulfadhli: Last week I went on to the Apple site to price out a MacPro that's set up like my next "desired" rig. The cost with a current i7 2600 was over 8 grand. At those prices Steve Jobs can use his Z68s chips to dip in salsa as far as I'm concerned.
| halfcalf wrote :
|
These boards have been selling in China for over 2weeks now.I am surprised why US hasnt even begun to sell their z68 chipsets..
Is there enough space on the (ATX) motherboard? 
Yep, 96/8 = 12, so it could use 12. I'd be surprised to see it in a normal MB though. From the 'leaks' so far, it looks like only 4 DIMMS. It would be nice if they could at least get 8 DIMMs on there, but even that would be a bit cramped.
Reply to EXT64
Heck, I don't care if the motherboard has to be the size of a pool table, I'd do anything for 12 RAM slots.
In the old days there were a lot of differences between Xeon systems and regular PCs, such as the 771-775 slot, registered memory, etc. With the SB-Es I can't see a single frickin' thing that really differentiates the i7 (or i9?) systems from the Xeons, other than they may be internally configured to go into dual or quad socket mobos. So since I'm seriously considering the possibility of selling my blood and living on bread and water between now and the end of the year, what would be the drawbacks to setting up my own personal system on an SB-E Xeon single socket and the least expensive mobo with those 12 luscious RAM slots?
Reply to halfcalf
| bruce555 wrote : Heat is a huge issue right now, temps of 80-90C under non OC full load are insane. It's the same sort of general thinking that I was talking about when it comes to size that they will still push the thermal threshold as well. Remember when the 6800 Ultra came out it was a ugly jump from the sub x800 series from ATI for dual slot cooler with a 400+ Watt PSU requirement. Even the OC'd 9800 xt's were single slot tiny fan's.
|
Heh, I'm still using my ancient GTX8800 which draws around 160 watts full-load, no oc. Bought a 5770 to upgrade but went back to the 8800 due to my Nvidia chipset having issues with ATI drivers, or else it's XP's fault, or both .
With high-end GPUs, I think the power draw will remain at 250 - 300 watts even with process shrinks, simply because that's what gamers are used to putting up with and new games will require more processing power. So the die shrinks/process advances will go to raise the latter while keeping the former about the same..
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