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How width of data & address buses affect CPUs performance & complexity

Could someone explain me please how the width of address and data buses can affect on processor performance and complexity?
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    The bandwidth or maximum theoretical throughput of the front-side bus is determined by the product of the width of its data path, its clock frequency (cycles per second) and the number of data transfers it performs per clock cycle. For example, a 64-bit (8-byte) wide FSB operating at a frequency of 100 MHz that performs 4 transfers per cycle has a bandwidth of 3200 megabytes per second (MB/s):
    http://en.wikipedia.org/wiki/Front-side_bus
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