I just had a thought about the cache for cpus. If as you increase the ways of a cache there is more chance to have a cache miss, wouldn't it be better to have a cache to store where the data could be in the cache? This would allow for a seamless flow if the processor could read from this cache while reading/writing to the actual cache.
It seems like a simple idea, so there must be more to this than just what I'm thinking; it seems like this secondary cache wouldn't need to be all that big, since it would just hold 'pointers' to where the data is in the cache thus this could just be a one-way cache to allow 100% accuracy, or even for the bigger caches, such as L3, which might need more of this pointer cache, two/four way would have a better chance of hitting then the big 16-way L3 cache in modern x86 procs.
Could anyone explain what might be the problems with this?
It seems like a simple idea, so there must be more to this than just what I'm thinking; it seems like this secondary cache wouldn't need to be all that big, since it would just hold 'pointers' to where the data is in the cache thus this could just be a one-way cache to allow 100% accuracy, or even for the bigger caches, such as L3, which might need more of this pointer cache, two/four way would have a better chance of hitting then the big 16-way L3 cache in modern x86 procs.
Could anyone explain what might be the problems with this?