i have older but good ecs ka3mvp crossfire board , no onboard video. It works good with 512 mb pcie x16 boards. I have used three different ones. When I install an ATI radeon hd5550 card it will not get past the post and fire up the os.Must hit F1 to bypass checksum error. I have tried and used various methods of trying to correct but to no avail. reset post via jumper, reflashed bios several different ways, ( this board has TOP HAT FLASH ). Works fine if i hit F1 and continue,but a real pain each time to startup or reboot. So the question is ta dah,,, is there a operational difference between PCIE X16 and PCIE X16 2.0 THANKS IN ADVANCE FOR A SANE ANSWER
iam2thecrowe
Glorious
- Jul 4, 2010
- 10,591
- 21
- 44,965
it has been reported that pcie 2.1 cards (all radeon 5xxx and 6xxx series are 2.1) have incompatabilities with some older pcie 1.x motherboards. Check for a recent BIOS update for your motherboard. If that doesnt work im afraid you will either need to find a pcie 2.0 video card or a new motherboard.
History
While in development, PCIe was initially referred to as HSI (for High Speed Interconnect), and underwent a name change to 3GIO (for 3rd Generation I/O) before finally settling on its PCI-SIG name PCI Express. It was first drawn up by a technical working group named the Arapaho Work Group (AWG) which, for initial drafts, consisted of an Intel only team of architects. Subsequently the AWG was expanded to include industry partners.
PCIe is a technology under constant development and improvement. The current PCI Express implementation is version 3.0.
[edit]
PCI Express 1.0a
In 2003, PCI-SIG introduced PCIe 1.0a, with a data rate of 250 MB/s and a transfer rate of 2.5 GT/s.
[edit]
PCI Express 1.1
In 2005, PCI-SIG introduced PCIe 1.1. This updated specification includes clarifications and several improvements, but is fully compatible with PCI Express 1.0a. No changes were made to the data rate.
[edit]
PCI Express 2.0
PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007.[10] The PCIe 2.0 standard doubles the per-lane throughput from the PCIe 1.0 standard's 250 MB/s to 500 MB/s. This means a 32-lane PCI connector (x32) can support throughput up to 16 GB/s aggregate. The PCIe 2.0 standard uses a base clock frequency of 2.5 GHz, while the first version operates at 1.25 GHz.
PCIe 2.0 motherboard slots are fully backward compatible with PCIe v1.x cards. PCIe 2.0 cards are also generally backward compatible with PCIe 1.x motherboards, using the available bandwidth of PCI Express 1.1. Overall, graphic cards or motherboards designed for v 2.0 will be able to work with the other being v 1.1 or v 1.0.
The PCI-SIG also said that PCIe 2.0 features improvements to the point-to-point data transfer protocol and its software architecture.[11]
Intel 's first PCIe 2.0 capable chipset was the X38 and boards began to ship from various vendors (Abit, Asus, Gigabyte) as of October 21, 2007.[12] AMD started supporting PCIe 2.0 with its AMD 700 chipset series and nVidia started with the MCP72.[13]All of Intel's prior chipsets, including the Intel P35 chipset, supported PCIe 1.1 or 1.0a.[14]
[edit]
PCI Express 2.1
PCI Express 2.1 supports a large proportion of the management, support, and troubleshooting systems planned to be fully implemented in PCI Express 3.0. However, the speed is the same as PCI Express 2.0. Most motherboards sold currently come with PCI Express 2.0 connectors.
[edit]
PCI Express 3.0
PCI Express 3.0 Base specification revision 3.0 was made available in November 2010, after multiple delays. In August 2007, PCI-SIG announced that PCI Express 3.0 would carry a bit rate of 8 gigatransfers per second, and that it would be backwards compatible with existing PCIe implementions. At that time, it was also announced that the final specification for PCI Express 3.0 would be delayed until 2011,[15] although more recent sources (see below) stated that it may be available towards the end of 2010. New features for the PCIe 3.0 specification include a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies.[16]
Following a six-month technical analysis of the feasibility of scaling the PCIe interconnect bandwidth, PCI-SIG's analysis found out that 8 gigatransfers per second can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) to the PCIe protocol stack.
PCIe 2.0 delivers 5 GT/s, but employs an 8b/10b encoding scheme which results in a 20 percent overhead on the raw bit rate. PCIe 3.0 removes the requirement for 8b/10b encoding and instead uses a technique called "scrambling" in which "a known binary polynomial is applied to a data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by running it through a feedback topology using the inverse polynomial"[17] and also uses a 128b/130b encoding scheme, reducing the overhead to approximately 1.5%, as opposed to the 20% overhead of 8b/10b encoding used by PCIe 2.0. PCIe 3.0's 8 GT/s bit rate effectively delivers double PCIe 2.0 bandwidth. According to an official press release by PCI-SIG on 8 August 2007:
"The final PCIe 3.0 specifications, including form factor specification updates, may be available by late 2009, and could be seen in products starting in 2010 and beyond."[18]
As of January 2010, the release of the final specifications had been delayed until Q2 2010.[19] PCI-SIG expects the PCIe 3.0 specifications to undergo rigorous technical vetting and validation before being released to the industry. This process, which was followed in the development of prior generations of the PCIe Base and various form factor specifications, includes the corroboration of the final electrical parameters with data derived from test silicon and other simulations conducted by multiple members of the PCI-SIG.
On May 31, 2010, it was announced that the 3.0 specification would be coming in 2010, but not until the second half of the year.[20] Then, on June 23, 2010, the PCI Special Interest Group released a timetable showing the final 3.0 specification due in the fourth quarter of 2010.[21]
Finally, on November 18, 2010, the PCI Special Interest Group officially publishes the finalized PCI Express 3.0 specification to its members to build devices based on this new version of PCI Express.[22]
cut and pasted from wikipedia...
While in development, PCIe was initially referred to as HSI (for High Speed Interconnect), and underwent a name change to 3GIO (for 3rd Generation I/O) before finally settling on its PCI-SIG name PCI Express. It was first drawn up by a technical working group named the Arapaho Work Group (AWG) which, for initial drafts, consisted of an Intel only team of architects. Subsequently the AWG was expanded to include industry partners.
PCIe is a technology under constant development and improvement. The current PCI Express implementation is version 3.0.
[edit]
PCI Express 1.0a
In 2003, PCI-SIG introduced PCIe 1.0a, with a data rate of 250 MB/s and a transfer rate of 2.5 GT/s.
[edit]
PCI Express 1.1
In 2005, PCI-SIG introduced PCIe 1.1. This updated specification includes clarifications and several improvements, but is fully compatible with PCI Express 1.0a. No changes were made to the data rate.
[edit]
PCI Express 2.0
PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007.[10] The PCIe 2.0 standard doubles the per-lane throughput from the PCIe 1.0 standard's 250 MB/s to 500 MB/s. This means a 32-lane PCI connector (x32) can support throughput up to 16 GB/s aggregate. The PCIe 2.0 standard uses a base clock frequency of 2.5 GHz, while the first version operates at 1.25 GHz.
PCIe 2.0 motherboard slots are fully backward compatible with PCIe v1.x cards. PCIe 2.0 cards are also generally backward compatible with PCIe 1.x motherboards, using the available bandwidth of PCI Express 1.1. Overall, graphic cards or motherboards designed for v 2.0 will be able to work with the other being v 1.1 or v 1.0.
The PCI-SIG also said that PCIe 2.0 features improvements to the point-to-point data transfer protocol and its software architecture.[11]
Intel 's first PCIe 2.0 capable chipset was the X38 and boards began to ship from various vendors (Abit, Asus, Gigabyte) as of October 21, 2007.[12] AMD started supporting PCIe 2.0 with its AMD 700 chipset series and nVidia started with the MCP72.[13]All of Intel's prior chipsets, including the Intel P35 chipset, supported PCIe 1.1 or 1.0a.[14]
[edit]
PCI Express 2.1
PCI Express 2.1 supports a large proportion of the management, support, and troubleshooting systems planned to be fully implemented in PCI Express 3.0. However, the speed is the same as PCI Express 2.0. Most motherboards sold currently come with PCI Express 2.0 connectors.
[edit]
PCI Express 3.0
PCI Express 3.0 Base specification revision 3.0 was made available in November 2010, after multiple delays. In August 2007, PCI-SIG announced that PCI Express 3.0 would carry a bit rate of 8 gigatransfers per second, and that it would be backwards compatible with existing PCIe implementions. At that time, it was also announced that the final specification for PCI Express 3.0 would be delayed until 2011,[15] although more recent sources (see below) stated that it may be available towards the end of 2010. New features for the PCIe 3.0 specification include a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies.[16]
Following a six-month technical analysis of the feasibility of scaling the PCIe interconnect bandwidth, PCI-SIG's analysis found out that 8 gigatransfers per second can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) to the PCIe protocol stack.
PCIe 2.0 delivers 5 GT/s, but employs an 8b/10b encoding scheme which results in a 20 percent overhead on the raw bit rate. PCIe 3.0 removes the requirement for 8b/10b encoding and instead uses a technique called "scrambling" in which "a known binary polynomial is applied to a data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by running it through a feedback topology using the inverse polynomial"[17] and also uses a 128b/130b encoding scheme, reducing the overhead to approximately 1.5%, as opposed to the 20% overhead of 8b/10b encoding used by PCIe 2.0. PCIe 3.0's 8 GT/s bit rate effectively delivers double PCIe 2.0 bandwidth. According to an official press release by PCI-SIG on 8 August 2007:
"The final PCIe 3.0 specifications, including form factor specification updates, may be available by late 2009, and could be seen in products starting in 2010 and beyond."[18]
As of January 2010, the release of the final specifications had been delayed until Q2 2010.[19] PCI-SIG expects the PCIe 3.0 specifications to undergo rigorous technical vetting and validation before being released to the industry. This process, which was followed in the development of prior generations of the PCIe Base and various form factor specifications, includes the corroboration of the final electrical parameters with data derived from test silicon and other simulations conducted by multiple members of the PCI-SIG.
On May 31, 2010, it was announced that the 3.0 specification would be coming in 2010, but not until the second half of the year.[20] Then, on June 23, 2010, the PCI Special Interest Group released a timetable showing the final 3.0 specification due in the fourth quarter of 2010.[21]
Finally, on November 18, 2010, the PCI Special Interest Group officially publishes the finalized PCI Express 3.0 specification to its members to build devices based on this new version of PCI Express.[22]
cut and pasted from wikipedia...
iam2thecrowe
Glorious
- Jul 4, 2010
- 10,591
- 21
- 44,965
The brochure may say 2.0, but its really a 2.1 card. http://ixbtlabs.com/articles3/video/juniper-p2.html some more details on pcie 2.1
swifty_morgan
Illustrious
- Feb 10, 2006
- 13,566
- 1
- 42,960
I have a 5850 with a 2.1 interface. Works fine on an A8N sli 32 deluxe mobo ( pci-e 1.0 ) and others.
The checksome error. You mess around inside the case and knock wires loose. Check HD wires.
The checksome error. You mess around inside the case and knock wires loose. Check HD wires.
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