blazorthon :
Also, each chip's actual frequency is a fraction of the frequency of the input/output bus which runs at a frequency as measured in MHz that is one fourth of its transfer rate as measured in MT/s. I don't know the ratios for GDDR5, but I do know them for DDR3 and DDR4. I think that DDR4 and GDDR5 chips with the same bandwidth run at the same actual frequency, just with GDDR5 running the input/output bus at four times faster than the chip's internal frequency and one fourth of the transfer rate (transfer rate is sixteen times greater than the chip frequency) and DDR4 instead has the input/output bus running at eight times the actual chip frequency and one half of the transfer rate (still sixteen times the actual chip frequency).
Basically, a DDR3 chip on a module marketed as 1600MHz is actually running at 200MHz, the input/output bus is running at 800MHz, and this bus transfers data on both the rising and falling edge of the clock, so you get 1600MT/s, marketed as 1600MHz to not confuse tech newbie people. This I can confirm. I believe that GDDR5 does the same thing, just with a quadruple data rate on it's input/output frequency instead of a double data rate, and DDR4 goes the simpler, cheaper route of doubling the input/output frequency instead of the data rate of that frequency to get similar performance per chip as GDDR5.
So, in order for GDDR5's input/output frequency to be four times greater than the internal frequency of each chip, it needs an 8 bit wide prefetch. A 2 bit wide prefetch would leave it more similar to the first generation DDR SDRAM interface, except with a quadruple data rate on the input/output bus instead of a double data rate, so it would perform more like a less efficient form of DDR2.
I'm not a RAM engineer, so don't hold me to this, but I think that it at least gives you an idea for what to look for. Another thing that I can confirm is that GDDR5 is at least partially based on DDR3. If you find anything, would you mind PMing me or posting in this thread? I'd like to get caught up on this and you seem like you've at least got something going here.
Thank you for your reply. Based on what I know you're correct with the things you say and you even ended up with my same doubt!
Let me explain...
Basically having a data rate being double, quadruple or octuple the internal clock frequency (as in DDR, DDR2 and DDR3 respectively) relies on a tecnique called pre-fetch buffering.
The idea is the same, to access a word in a memory I have to access to a row which contains multiples words. When I access to a row, I get
simultaneous access to multiple words.
I can use a multiplexer with a column address to choose a single word out of the row and write it on the data bus, but that's not efficient considering that the next word the CPU is probably gonna need is the next one in the same row which I already had available in first place.
So we want to take advantage of the fact that we have multiple words available after a RAS signal. How?
Basically once a full row is ready, in the next clock cycle we can take a few words (how many depends on the burst level we want to achieve) out of the row and write them simultaneously in a buffer which acts as a queue at a bit line level.
If we take 2 words simultaneously out of a row, we will need a 2 bit buffer for each bit line of the data bus.
If we take 4 words, a 4 bit buffer for each bit line.
8 words, 8 bit buffer.
This queue will be emptied at a speed which is a multiple of the clock frequency so that all the words queued will be out in a single clock cycle (in time to receive the next batch of words to be transmitted or to end the read operation).
So we'll get 2 words out in a single clock cycle for DDR, 4 for DDR2 and 8 for DDR3.
In a DDR memory the timings of the signals which control the queue buffer (or pre-fecth buffer) are such that the data trasmissions on the bus are synchronized with both the fronts of the internal clock.
In DDR2 each clock cycle, on each bit line 4 bit are trasmitted, those transmissions are synchronized with a signal which is double the frequency of the internal clock and on both fronts (alternatively they can be seen as synchronized with a signal which is 4 times the frequency of the internal clock but on a single front).
DDR3 is the same thing. The data trasmissions happen on both fronts of a clock signal with quadruple the frequency of the internal clock or on single fronts of a clock with 8x the internal frequency.
Now on to the GDDR5.
As far as I could get from the data sheets, this memory has a claimed DATA RATE (not the I/O frequency) of 4 times the internal clock cycle (which means that I/O frequency is 2 times the internal clock frequenct but with trasmissions on both fronts).
In fact to calculate the bandwidth of GDDR5 memory used on graphics cards the formula is CK*4*(bus width/8).
The difference between this memory and DDR3 is that words are sent out of a row with a WCK signal which is double the internal clock and the burst level is claimed to be 2x, so for each bit line, two bits are taken out of the memory in a WCK period which is half the CK period.
So basically to me this memory seems just like a DDR memory where the (2) words are read out of the memory at double the clock frequency. So effectively it's a DDR2, with a data rate being 4 times the internal clock.
It would only need a 2 bit buffer to achieve that data rate....yet......it has a 8 bit buffer like DDR3 which seems useless to me if you only take two words simultaneously out of memory banks. To take advantage of it we should take 8 words simultaneously in a WCK period. But that would lead to a data rate 16X the internal clock, while the data rate is claimed to be just 4X.
So in this whole mess I guess that I got something wrong...maybe it's better to go to the beach
:lol: :lol: :lol: :lol:
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