Bulldozer's IPC Death- "1000 little cuts"

Now that Bulldozer is out in the wild, and we've had a few days to digest what it is, this thread will be about Bulldozer's foundation and what it might lead to.

I have two articles for everyone to read before they start the flamewars :
http://semiaccurate.com/2011/10/17 [...] nderwhelm/
http://semiaccurate.com/2011/10/17 [...] e-problem/
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It seems that Bulldozer is a very unfinished product as many forum members have been saying.

There are many quirks with Bulldozer that I do not like. Charlie seems to have the same idea on a few things as I do.

The decode stage is up with 4 decoders to feed the cores, but overall the decoded instructions is down per core. It was 3 in Phenom II and is now 2 in Bulldozer. I thought that this would be no big deal mostly due to improvements elsewhere, but that didn't happen. Only two math instructions happen in the integers at one time in a core compared to 3 max in Phenom. Usually this isn't a big deal; the program might not use that third out of order integer core, but it can affect performance in situations that it does.

L1 and L2 cache latency is up; not just a little. L1 is up 1 cycle, that is a 33% increase in latency for a smaller L1 cache. L2 cache is around 25-27 cycles, a near 70% increase over Phenom! What were they thinking allowing these terrible latencies in Bulldozer's design? I agree with Charlie, they should have made the L2 cache at 1MB with lower latency. Instead they could've had that smaller L2 with the L3 as fillover for any extra instructions needed, much like Sandy Bridge.

It also appears that Glofo isn't totally to blame for Bulldozer's woes on clockspeed and power. There needs to be some fine tuning to the architecture before we see what Bulldozer was really meant to be speed wise; Piledriver might just be this finely tuned Bulldozer.
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What does everyone think about Bulldozer?

I would like to talk about the architecture if anyone wants to get down and dirty with me.

If things designed in an arch were made to do their job and shut down, but instead, it has to work harder, temps and clocks can be effected.
The cache cycles dont look good, and its slow anyways, and both Llano and BD have the same amount of cycles on the L2, and both have reached their curve power/perf, and its alot of uphill from there for power and heat, as the perf curve drops off

Nice assessment
There are differences between the 2 chips, and is probably why the cache size/heiarchy is different.
Alot can be done, I agree, and remember, this is first gen 32nm, and a whole new chip, a whole new approach.
I think theyll find what looks good in sims are different than real usage, and those adjustments will come

Sandy Bridges L3 cache latency- 26-31 cycles v. Bulldozer's L2 cache latency 25-27 cycles. Sure it's nearly the same latency, but Sandy Bridge's cache level is one higher!

So a single core has to go through the faster L1, the faster L2, then the L3 cache in Sandy Bridge. Bulldozer only hits its fast L1 before hitting a slow L2; they might as well shoot themselves in the foot right there.

I'm wondering why they made the L2 so big. The core would need good prediction to have small caches with high hit rates. I have seen what branching can do to Bulldozer's performance, and it's not pretty. I don't even think better prediction would increase performance all that much unless it was excellent. The only real increase on per core performance could be predicting instructions to fit into the L1 before they're needed, but the L1 is so small that it would be tough to keep getting correct predictions. Once you're at the L2, you're already done; no performance can be gained through prediction.

I don't think Bulldozer's foundation is strong enough to push Intel. They went for faster frequencies, but with a power/heat wall in their way.

Edit: grammar nazi

That would in fact improve performance over Bulldozer.

Increase L3 size while decreasing the cache latencies. Improve prediction for the core. Make the cache inclusive v. exclusive. Increase core count to 8. Bam, just made a Phenom III that outperforms Bulldozer.

When do people think Piledriver variants will be released?

Do you guys think that cache latency was increased due to increased in die size?
In SB due to it's smaller die size everything's cramped together and may be that's why the latency is low. (?)

I'm no pro but I think having only 4 Floating Point calculation modules is what to blame. I use resources heavy applications like Maya, 3ds Max and these applications use FPs for almost everything. Even media encoders use FPs (I'm guessing).
So technically for these applications, it's like having only four cores.
For such application bd is nothing but a four core hyper-threaded (4c/8t) CPU.

Anyway,
1. The six-core BD could out perform eight-core BD, if they physically remove disabled cores and put another 2 FP modules there. I know it can't be done overnight but still a food for thought.

2. AMD, most of the time stays ahead of Intel when it comes to introducing new stuff in CPUs like 64 bit architecture, good dual core implementation etc,. But was really necessary to have 128-bit FP modules ? How many applications go that far to use 128 bit architecture? Do SSE 2, 3 have capability to use that? (I'm asking because I've no idea). I think they sacrificed too much of the today's CPU foundation just to make it future-ready.

AMD's Bulldozer is like the orginal motor cars. Unreliable and not clearly better than the horse, but the motor car (Bulldozer) can be tuned into that beats the horse (K10.5).

I have heard Q3 2012 somewhere. Either way Trinity and Piledriver will meet IB head on, well not sure performance wise though.

I think the higher latencies actually stem from the longer pipeline. Of course I am no expert, although I have been through many tech classes that talk about this but the math always escaped me.

As for the Pentium 4, don't shun it too much. Intel took some things from NetBurst and put it towards the Core uarch and even SB (the Pentium 4 had trace cache, much like the micro-uOP buffer SB has.

I would say K8 was fine tuned. Not sure they could have sucked more out of it if they tried.

I believe it's due to the increase in pipeline depth and the size of the caches being increased.

1. Integer perf would go below a Thuban though!

2. 128-bit is actually used quite often in SSE enabled programs. I think it mostly gangs together 32-bit or 64-bit FP operations and executes them at the same time. It's AVX's 256-bit operations that won't be used for quite some time.

Maybe...but even with the gpu off it performs just slightly over the Athlon II. It would've been about the same if they just left it like an athlon II.

Oh yes, the prediction unit really catapults Intel ahead. Prediction also needs a finely tuned arch to go with it or it is just a waste- Pentium 4 shows that.

WAIT! how could anyone still be hoping to WAIT for something good from them. At best its going to be 13% faster according to AMD. Intel's CPU's are already more than 13% faster while only using 4 cores, and they have new CPU's launching any time now. The bulldozer architecture is a flop, i dont think any amount of tweaking can help it. They should just throw it away and start again and just sell higher clocked phenom II's for cheap.

I sorta think AMD should try to combine the best features of P2 and BD - 8 full cores, each with a faster 1MB L2 cache, 4-issue decoders, etc. Yeah it would be bigger than 315mm^2, but AMD is used to making huge die CPUs anyway it seems. Or else hurry up 22nm.

I do really think that BD is unfinished. AMD go pressured too much for a release of any CPU and they had to release BD before it was even ready. I am not sure that BD will be a competitive CPU, but I am sure that the next line up will be much better, but only time will tell unless there is an AMD employee around here who wont mind sharing some details with us.

That was JF-AMD. He recently posted over in the Anandtech forums about all the hate mail and flames he has been getting, so he has given up posting for the time being anyway, as he does it on his own time and can only post info that has been approved by the engineering team. Which is why he posted many months ago that IPC would be better on BD than prior architecture (P2).

2 possible things happened. Either he lied to us, OR he was lied to.

Once again, Barcelona and the x4 9600 black edition. Those who don't learn from history............

What does it take to make a desktop CPU scalable? If they just, if they just could design a chipset which could accumulate double bulldozer, only then it would be worthwhile to investment in them. I know it's not gonna happen

Workstation CPUs are very expensive.

The CPU isn't the problem, software is.

Until you get a programming language that actually lends itself to parallel applications implicity and an OS written in said language, you will almost never reach the dream of decent scalability.

I think you are going to see GPUs come more to the forefront, simply because they are designed to handle massivly parallel applications, unlike CPU's, which still are best handling a few things at one time, but at a very fast speed. They complement eachother.

My take is, too many little problems like Charlie suggests, which if unattended to, can cause alot of power and heat problems.
As for JF, things changed on him, as you could tell by his latter posts, where the IPC issue simply wasnt addressed by him, as by the time it was truly ready, he knew, had said too much of planned ideals, and surely couldnt back off and change what hed said earlier, not his fault.
It seems both Intel and AMD do extremely well with a known arch, and Intel starts and finishes a tad longer than AMD, and have more resources to throw at it as well.
That being the case, the new CEO is forming a tick tock of sorts at AMD, will it succeed, well, good thing is, BD arch is a good one, much to build upon, which allows for familiarity, which AMD does do well at.

The sim tools and time arent AMDs friends, plus a slight harder crunch coming from GF, with its early problems, a snowball effect.
My 2c

Most of the software I use can scale upto 128 cores or more. That's why I was eagerly hoping for some kick ass performance from BD as I can't afford multi workstation cpu setup right now.
Software like Maya can run on a super computer having thousands of processors.
My needs are a little different.

I don't think either one. Last year, before all the problems were known, the engineers probably assured JF that IPC would improve according to their simulations. Then as various problems surfaced, they stopped telling him that. Unfortunately, JF is limited as to what he can tell us, so I think he sorta hinted that maybe IPC wouldn't improve by discounting its importance, and instead emphasizing multi-core performance. After all, he is director of server marketing and thus he is not going to emphasize problems but advantages as much as he can. You just have to read between the lines and pay attention to not only what he does say, but what he doesn't (or no longer) says..

Similar to mine it sounds like. Because Maya, etc are hardcore apps, they will get the XOP\AVX\FMAC treatment first. That's where BD shines RIGHT NOW.

After reading several posts, MEH, not going to bother with this. I just find it amazing when people become CPU gurus. Almost like over night.

I looked that up, and I can't believe that each module can only use 2MB of the L3 each. The L3 is totally inclusive of the L2 to prevent major snoop traffic in the cores, so it helps highly threaded workloads but sucks on lightly threaded workloads. AMD needs to rethink their cache.

Perhaps the 4150 will scale a little better if each module can use 4MB then.

Dirk was wise to stop this from being released earlier; it's still not ready. Now I'm thinking even Piledriver won't fix enough flaws to make it compete against Ivy Bridge; the foundation is rotten...

I see why Cray bought up the chips though; it really is a good HPC chip meant for very parallel workloads.

CPUs aren't as good as GPUs for parallel though. They should stick with serial strength on the CPU and parallel strength on the GPU with their APU strategy.

This discussion of the BD failings is all well and good; however, is there a realistic way to improve upon this BD architecture and have a viable desktop competitor to SB in the Windows 7, 8 market?

I notice in another blog the announcement of a B3 revision linked to an errata page.Since the BD B2 was just released, how long will it take for a B3 release? Or will this follow the path of the original Phenom and then the Phenom II?

I would actually like comments from everybody on this if you don't mind.

What is the difference between the XOP and AVX codepath for Bulldozer? I've heard that it performs just about the same, but I don't know much about XOP.