Umm...you got it backwards; you need to ENABLE Memory Remapping, not disable.http://en.wikipedia.org/wiki/3_GB_barrier
Modern personal computers are built around a set of standards that depend on, among other things, the characteristics of the original PCI bus. The original PCI bus supported 32-bit physical addresses and 32-bit wide data transfers. PCI (and PCI Express, and AGP) devices present at least some, if not all, of their host control interfaces via a set of memory-mapped I/O locations (MMIO). The address space in which these MMIO locations appear is the same address space as that used by RAM, and while RAM can exist and be addressable above the 4 GB point, these MMIO locations decoded by I/O devices cannot be. They are limited by PCI bus specifications to addresses of 0xFFFFFFFF (232-1) and below. With 4 GB or more of RAM installed, and with RAM occupying a contiguous range of addresses starting at 0, some of the MMIO locations will overlap with RAM addresses.
The BIOS and chipset are responsible for detecting these address conflicts and disabling access to the RAM at those locations. Due to the way bus address ranges are determined on the PCI bus, this disabling is often at a relatively large granularity, resulting in relatively large amounts of RAM being disabled.
x86 chipsets that support more than 4 GB of RAM typically also support memory remapping (referred to in some BIOS setup screens as "memory hole remapping"). In this scheme, the BIOS detects the memory address conflict and in effect relocates the interfering RAM so that it may be addressed by the processor at a new physical address that does not conflict with MMIO. On the Intel side, this support once was limited to server chipsets; however, newer desktop chipsets like the Intel 955X and 965 and later support it as well. On the AMD side, the AMD K8 and later processors' built-in memory controller supported it from the beginning.