"AMD Waits For 65nm To Crank Up The Megahertz"

[9-inch]

So what can we expect from the first 65 nm parts off the line? Probably something that few folks actually expect. Let me delve into one of the more overlooked properties of transistor design (well, at least to laymen like me). Basically the more stages in a pipeline means that the propagation delay in a signal is cut down and overall clockspeed can be increased, but more stages means that more transistors are being used. AMD is working with several partners to make sure that its 65 nm process is world class. This process encompasses embedded SiGe with dual stress liner and stress memorization technology on silicon on insulator- or e-SiGe with DSL and SMT on SOI for those so inclined. AMD and IBM have stated publicly that this technology allows for a 40% faster switching transistor than from a standard 65 nm design without all the three letter acronyms (TLA’s). In a complex design like a CPU this could mean a theoretical 50% overall clockspeed increase going from AMD’s 90 nm process to AMD/IBM’s 65 nm process all the while staying within the same power envelope.

So, for AMD’s first 65nm design, it had several choices. The first and most conservative choice would be to keep the Rev. F design essentially intact and port it to 65nm and explore the upper boundaries of clockspeed while taking a page from Intel’s Pentium 4 book.

The second choice would be similar to what NVIDIA did with the 90nm G7x series and reduce the transistor count and die size, while improving the clockspeed by a smaller amount.

The final choice would be to transition those extra transistors in those redundant stages into more useful units, and increase IPC all the while keeping clockspeed in the same general area that current 90 nm processors enjoy, all the while shrinking the die size to more manageable levels. This final choice appears to be what AMD has in mind.

http://www.theinquirer.net/?article=32322

 

[Heyyou27]

Let's hope they don't go prescott on it.

 

[Mardark]

Quick Summary:

The approach to 65 nm that AMD is taking, isn't going to give them a big speed boost.

We will have to wait til spring 2007 when K8L comes out, to see any big AMD performance leaps.

There, I saved you the trouble of reading it.....

 

[ltcommander_data]

I'm still curious as to the point in AMD adding a 4th complex decoder to the K8 architecture. Usually adding an extra decoder requires a massive redesign in order to take advantage of it. In this case, AMD did no such thing with the execution units, bus widths, etc. remaining exactly the same. The new out of order buffers should improve the utility of the three current decoders further making the 4th one pointless. I suppose it's partly a test run for K8L and partly a marketing decision to match Intel. Any performance increase is welcome of course.

Still, although The Inquirer mentions them increasing clock speeds, that isn't apparent as 65nm chips will initially ship only in the low end X2s at current clock speeds. The FX64 will run at 3GHz, but it is still a 90nm chip. With the 65nm chips coming at low clock speeds in December, and K8L launching in the Spring, I wonder when AMD really plans to ramp clock speeds on this modified K8?

 

[BaronMatrix]

Quick Summary:

The approach to 65 nm that AMD is taking, isn't going to give them a big speed boost.

We will have to wait til spring 2007 when K8L comes out, to see any big AMD performance leaps.

There, I saved you the trouble of reading it.....

I saw a site today that showed a die pic comparing Rev F to Rev G and it seem sto imply that there is an extra decoder and what "looks like" an OoO buffer. I'll look for the site link.

IF so there's a possible 10-15% boost. It shouldn't cost them much to update individual sections according to their "modular" approach and they have learned from Intel that you can't just "leap ahead" without leaving most of your inventory in a lurch.

I would hope that they avoid this price war but it seem slike they're going to go for it. In my opinion so what Intel is slashing prices. A64 is STILL worth the money. I have used both and for heavy use, Athlon is supreme. Hopefully Core 2 will not be cursed by the "clean install"

 

[BaronMatrix]

I'm still curious as to the point in AMD adding a 4th complex decoder to the K8 architecture. Usually adding an extra decoder requires a massive redesign in order to take advantage of it. In this case, AMD did no such thing with the execution units, bus widths, etc. remaining exactly the same. The new out of order buffers should improve the utility of the three current decoders further making the 4th one pointless. I suppose it's partly a test run for K8L and partly a marketing decision to match Intel. Any performance increase is welcome of course.

Still, although The Inquirer mentions them increasing clock speeds, that isn't apparent as 65nm chips will initially ship only in the low end X2s at current clock speeds. The FX64 will run at 3GHz, but it is still a 90nm chip. With the 65nm chips coming at low clock speeds in December, and K8L launching in the Spring, I wonder when AMD really plans to ramp clock speeds on this modified K8?

it will be interesting to see it play, but what it seem sliek is they do't want to be too much better than their current stock. Especially considering that Intel will bleed billions just to hurt AMD.

They have been talking about "modularity" so maybe it extends to how they connect the decoders to the instruction units. As far as clock speed they may choose to differentiate the server and desktop chips by that also, along with number of cores. Imean looking at how well Opteron OC at 90nm they should be easily run around 4GHz on 65nm.

It's possible they will keep the desktop under 3.2GHz and the server above at first and then move up gradually.

 

[9-inch]

I saw a site today that showed a die pic comparing Rev F to Rev G and it seem sto imply that there is an extra decoder and what "looks like" an OoO buffer. I'll look for the site link.

Don't worry.

The extra hardware in between the L2 cache and the data cache is likely an out-of-order L2 read/write buffer that expedites data neeeded for execution. The large bank on the other side of the data cache would be the logical placement for an out-of-order load/store buffer. This prevents cache misses from waiting on Stores to main memory. The extra complex decoder was spotted by a poster on some website. It was the first feature that caught my eye. This shot is definitely not of K-8. Given the layout of the additions, their functions can be inferred.

Granted the two shots are using a different stain and features can appear very different, it's intriguing. A lot of other features look radically different in this stain and may or may not have been actually changed, so don't bank on this.

http://129.15.202.185/athlon_rev_g/wtf_mates.html

 

[9-inch]

You can bet on it!

 

[tmac]

:twisted: Intel should bet on it also, since Conroe is just the beginning.
This a lot of room to grow, or make mistakes, in throwing a lot of cores
together and making it work in harmony.

 

[chuckshissle]

That's all good news to everyone and hope it would be something cheaper and better that the last architecture.

 

[Parrot]

So what can we expect from the first 65 nm parts off the line? Probably something that few folks actually expect. Let me delve into one of the more overlooked properties of transistor design (well, at least to laymen like me). Basically the more stages in a pipeline means that the propagation delay in a signal is cut down and overall clockspeed can be increased, but more stages means that more transistors are being used. AMD is working with several partners to make sure that its 65 nm process is world class. This process encompasses embedded SiGe with dual stress liner and stress memorization technology on silicon on insulator- or e-SiGe with DSL and SMT on SOI for those so inclined. AMD and IBM have stated publicly that this technology allows for a 40% faster switching transistor than from a standard 65 nm design without all the three letter acronyms (TLA’s). In a complex design like a CPU this could mean a theoretical 50% overall clockspeed increase going from AMD’s 90 nm process to AMD/IBM’s 65 nm process all the while staying within the same power envelope.

So, for AMD’s first 65nm design, it had several choices. The first and most conservative choice would be to keep the Rev. F design essentially intact and port it to 65nm and explore the upper boundaries of clockspeed while taking a page from Intel’s Pentium 4 book.

The second choice would be similar to what NVIDIA did with the 90nm G7x series and reduce the transistor count and die size, while improving the clockspeed by a smaller amount.

The final choice would be to transition those extra transistors in those redundant stages into more useful units, and increase IPC all the while keeping clockspeed in the same general area that current 90 nm processors enjoy, all the while shrinking the die size to more manageable levels. This final choice appears to be what AMD has in mind.

http://www.theinquirer.net/?article=32322

ENJOY!!

 

[ltcommander_data]

I was wondering this and I've doubled checked and confirmed. That supposed Rev G die image that is being bandied about with 4 complex decoders is not Rev G. In fact, it's nothing more than a production prototype for K8L.

http://pc.watch.impress.co.jp/docs/2006/0531/kaigai273.htm

Translated:
http://www.google.ca/translate?u=http%3A%2F%2Fpc.watch.impress.co.jp%2Fdocs%2F2006%2F0531%2Fkaigai273.htm&langpair=ja%7Cen&hl=en&ie=UTF8

If you look at the image with the three die images, you'll notice the centre one with 4 decoders is crossed out. The fact that that is not the real Rev G is consistant with what I've been saying on the subject before. Here is what Dirk Meyer, the President of AMD has to say on the subject:

On in figure (CPU core) Rev. F is. Center with production prototype, Rev. It is not G. You under Rev. As for those which are called H, we 'Hound (the hound)' with are one among the next generation cores which are called

It's a little garbled because of the translator, but essentially the first core is Rev F, the core in the centre is Rev _ because it's merely a prototype, and the die plot below Rev _ is Rev H, the Hound core or K8L.

With G, Rev. There are no extensions from F.

As for G you say that it is the core which almost is close to optical shrinking.

Rev G will be a simple die shrink, and while there may be a few tweaks to the memory controller and improved power control, it will be essentially the same as Rev F.

My opinion of PC Watch Impress is pretty good and the fact that the President of AMD makes these statements about the Rev _ being nothing more than a prototype makes it quite likely. Certainly AMD has never labelled that blue tinged die shot Rev G, that was just speculation on other people's part. I don't believe AMD has shown any die shot or die plot of Rev G, only that they demonstrated a working system and a wafer. The likelihood of the blue shot being Rev G was low anyways given reasons I mentioned before, namely the uselessness of the 4th complex decoder, lack of reported performance increase with the chips retaining the same names at same clocks as Rev F, no marketing from AMD, apparent closeness of K8L, unliklihood of launching large architecture changes at the same time as a process change, etc.

 

[9-inch]

Rev G will be a simple die shrink, and while there may be a few tweaks to the memory controller and improved power control, it will be essentially the same as Rev F.

I differ with you on this one. I don't think Rev. G is just a die shrink as you state. I believe rev g will be a short term answer from AMD to counter conroe once K8L sees the light of day. Once K8L debuts, rev G will be destined to replace the low end segment (i.e. Sempron).
Rev G doesn't have all the enhancements that K8L has since you also state that those Rev g pics are K8L prototypes.

Let's wait a bit more for additional info on this topic.

 

[BaronMatrix]

I was wondering this and I've doubled checked and confirmed. That supposed Rev G die image that is being bandied about with 4 complex decoders is not Rev G. In fact, it's nothing more than a production prototype for K8L.

http://pc.watch.impress.co.jp/docs/2006/0531/kaigai273.htm

Translated:
http://www.google.ca/translate?u=http%3A%2F%2Fpc.watch.impress.co.jp%2Fdocs%2F2006%2F0531%2Fkaigai273.htm&langpair=ja%7Cen&hl=en&ie=UTF8

If you look at the image with the three die images, you'll notice the centre one with 4 decoders is crossed out. The fact that that is not the real Rev G is consistant with what I've been saying on the subject before. Here is what Dirk Meyer, the President of AMD has to say on the subject:

On in figure (CPU core) Rev. F is. Center with production prototype, Rev. It is not G. You under Rev. As for those which are called H, we 'Hound (the hound)' with are one among the next generation cores which are called

It's a little garbled because of the translator, but essentially the first core is Rev F, the core in the centre is Rev _ because it's merely a prototype, and the die plot below Rev _ is Rev H, the Hound core or K8L.

With G, Rev. There are no extensions from F.

As for G you say that it is the core which almost is close to optical shrinking.

Rev G will be a simple die shrink, and while there may be a few tweaks to the memory controller and improved power control, it will be essentially the same as Rev F.

My opinion of PC Watch Impress is pretty good and the fact that the President of AMD makes these statements about the Rev _ being nothing more than a prototype makes it quite likely. Certainly AMD has never labelled that blue tinged die shot Rev G, that was just speculation on other people's part. I don't believe AMD has shown any die shot or die plot of Rev G, only that they demonstrated a working system and a wafer. The likelihood of the blue shot being Rev G was low anyways given reasons I mentioned before, namely the uselessness of the 4th complex decoder, lack of reported performance increase with the chips retaining the same names at same clocks as Rev F, no marketing from AMD, apparent closeness of K8L, unliklihood of launching large architecture changes at the same time as a process change, etc.


Well, I think now we know that links aren't everything.

 

[ltcommander_data]

Rev G doesn't have all the enhancements that K8L has since you also state that those Rev g pics are K8L prototypes.

Well, it's not really what I state, it's that the President of AMD states that the centre picture is not Rev F so there are no Rev G pics. And you're right, more clarity on the subject would be nice.

 

[MU_Engineer]

AMD is a much smaller company than Intel is and has to play pretty conservatively to keep from getting too far into the red. They are likely rolling out lower-clocked 65nm X2 parts as 90nm is a very known quantity to them as far as yields and reliability and 65nm isn't. If the initial runs of 65nm parts see yields being good, then AMD will switch completely over as then it's a known good thing. If yields suffer, then AMD still has a lot of fab left on 90nm to make a lot of salable chips. If they went all 65nm and had a problem, they'd be in big trouble as they'd have few chips to sell and Fab 36 to pay off.

 

[MU_Engineer]

It had been pretty boring for Intel as they released basically two chips from 1995 to 2005: the Pentium Pro and the Pentium 4. AMD had the K6, K7 and K8. But since the beginning of 2005, we've seen dual core chips, a new architecture from Intel, quad cores coming shorty, and a new arch from AMD due in about a year.

I guess it gets interesting once the engineers have to actually work and not just shrink the same die and ramp up speeds